Single-Cycle-MIPS-Processor

Introduction :

In this project, you are required to implement a 32-bit single-cycle microarchitecture MIPS processor based on Harvard Architecture. The single-cycle microarchitecture executes an entire instruction in one cycle. In other words instruction fetch, instruction decode, execute, write back, and program counter update occurs within a single clock cycle.

Objective :

Referring to figure one, you are required to write the RTL Verilog files for all sub-modules of the MIPS processor (e.g. Register File, Instruction Memory, etc.). Then, implementing the top module of the MIPS processor. Finally, you will configure this processor on Cyclone® IV FPGA device.

Top_Module View :

Simulation Results

• Calculating the GCD of two Numbers (120 , 180)
• Calculating the Factorial of a given Number !7
• find fibonacci sequence