Skip to content

Commit

Permalink
VertexSet use vertex id for comparison
Browse files Browse the repository at this point in the history
Signed-off-by: James Cherry <[email protected]>
  • Loading branch information
jjcherry56 committed Mar 1, 2022
1 parent 783db41 commit 61c0f9d
Show file tree
Hide file tree
Showing 20 changed files with 265 additions and 240 deletions.
32 changes: 13 additions & 19 deletions dcalc/GraphDelayCalc1.cc
Original file line number Diff line number Diff line change
Expand Up @@ -214,6 +214,8 @@ GraphDelayCalc1::GraphDelayCalc1(StaState *sta) :
observer_(nullptr),
delays_seeded_(false),
incremental_(false),
delays_exist_(false),
invalid_delays_(new VertexSet(graph_)),
search_pred_(new SearchPred1(sta)),
search_non_latch_pred_(new SearchPredNonLatch2(sta)),
clk_pred_(new ClkTreeSearchPred(sta)),
Expand All @@ -226,6 +228,7 @@ GraphDelayCalc1::GraphDelayCalc1(StaState *sta) :
GraphDelayCalc1::~GraphDelayCalc1()
{
delete search_pred_;
delete invalid_delays_;
delete search_non_latch_pred_;
delete clk_pred_;
delete iter_;
Expand Down Expand Up @@ -293,7 +296,7 @@ GraphDelayCalc1::delaysInvalid()
incremental_ = false;
iter_->clear();
// No need to keep track of incremental updates any more.
invalid_delays_.clear();
invalid_delays_->clear();
invalid_check_edges_.clear();
invalid_latch_edges_.clear();
}
Expand Down Expand Up @@ -326,11 +329,11 @@ GraphDelayCalc1::delayInvalid(Vertex *vertex)
debugPrint(debug_, "delay_calc", 2, "delay invalid %s",
vertex->name(sdc_network_));
if (graph_ && incremental_) {
invalid_delays_.insert(vertex);
invalid_delays_->insert(vertex);
// Invalidate driver that triggers dcalc for multi-driver nets.
MultiDrvrNet *multi_drvr = multiDrvrNet(vertex);
if (multi_drvr)
invalid_delays_.insert(multi_drvr->dcalcDrvr());
invalid_delays_->insert(multi_drvr->dcalcDrvr());
}
}

Expand All @@ -339,7 +342,7 @@ GraphDelayCalc1::deleteVertexBefore(Vertex *vertex)
{
iter_->deleteVertexBefore(vertex);
if (incremental_)
invalid_delays_.erase(vertex);
invalid_delays_->erase(vertex);
MultiDrvrNet *multi_drvr = multiDrvrNet(vertex);
if (multi_drvr) {
multi_drvr->drvrs()->erase(vertex);
Expand Down Expand Up @@ -432,17 +435,15 @@ GraphDelayCalc1::findDelays(Level level)
void
GraphDelayCalc1::seedInvalidDelays()
{
VertexSet::Iterator vertex_iter(invalid_delays_);
while (vertex_iter.hasNext()) {
Vertex *vertex = vertex_iter.next();
for (Vertex *vertex : *invalid_delays_) {
if (vertex->isRoot())
seedRootSlew(vertex, arc_delay_calc_);
else {
if (search_non_latch_pred_->searchFrom(vertex))
iter_->enqueue(vertex);
}
}
invalid_delays_.clear();
invalid_delays_->clear();
}

class FindNetDrvrs : public PinVisitor
Expand Down Expand Up @@ -508,7 +509,7 @@ void
GraphDelayCalc1::makeMultiDrvrNet(PinSet &drvr_pins)
{
debugPrint(debug_, "delay_calc", 3, "multi-driver net");
VertexSet *drvr_vertices = new VertexSet;
VertexSet *drvr_vertices = new VertexSet(graph_);
MultiDrvrNet *multi_drvr = new MultiDrvrNet(drvr_vertices);
Level max_drvr_level = 0;
Vertex *max_drvr = nullptr;
Expand Down Expand Up @@ -549,11 +550,8 @@ GraphDelayCalc1::multiDrvrNet(const Vertex *drvr_vertex) const
void
GraphDelayCalc1::seedRootSlews()
{
VertexSet::Iterator root_iter(levelize_->roots());
while (root_iter.hasNext()) {
Vertex *vertex = root_iter.next();
for (Vertex *vertex : *levelize_->roots())
seedRootSlew(vertex, arc_delay_calc_);
}
}

void
Expand Down Expand Up @@ -919,9 +917,7 @@ GraphDelayCalc1::findDriverDelays(Vertex *drvr_vertex,
Vertex *dcalc_drvr = multi_drvr->dcalcDrvr();
if (drvr_vertex == dcalc_drvr) {
bool init_load_slews = true;
VertexSet::Iterator drvr_iter(multi_drvr->drvrs());
while (drvr_iter.hasNext()) {
Vertex *drvr_vertex = drvr_iter.next();
for (Vertex *drvr_vertex : *multi_drvr->drvrs()) {
// Only init load slews once so previous driver dcalc results
// aren't clobbered.
delay_changed |= findDriverDelays1(drvr_vertex, init_load_slews,
Expand Down Expand Up @@ -1381,9 +1377,7 @@ GraphDelayCalc1::findMultiDrvrGateDelay(MultiDrvrNet *multi_drvr,
{
ArcDelay delay_sum = 1.0;
Slew slew_sum = 1.0;
VertexSet::Iterator drvr_iter(multi_drvr->drvrs());
while (drvr_iter.hasNext()) {
Vertex *drvr_vertex1 = drvr_iter.next();
for (Vertex *drvr_vertex1 : *multi_drvr->drvrs()) {
Pin *drvr_pin1 = drvr_vertex1->pin();
Instance *drvr_inst1 = network_->instance(drvr_pin1);
LibertyCell *drvr_cell1 = network_->libertyCell(drvr_inst1);
Expand Down
2 changes: 1 addition & 1 deletion dcalc/GraphDelayCalc1.hh
Original file line number Diff line number Diff line change
Expand Up @@ -212,7 +212,7 @@ protected:
bool incremental_;
bool delays_exist_;
// Vertices with invalid -to delays.
VertexSet invalid_delays_;
VertexSet *invalid_delays_;
// Timing check edges with invalid delays.
EdgeSet invalid_check_edges_;
// Latch D->Q edges with invalid delays.
Expand Down
29 changes: 26 additions & 3 deletions graph/Graph.cc
Original file line number Diff line number Diff line change
Expand Up @@ -48,14 +48,18 @@ Graph::Graph(StaState *sta,
have_arc_delays_(have_arc_delays),
ap_count_(ap_count),
width_check_annotations_(nullptr),
period_check_annotations_(nullptr)
period_check_annotations_(nullptr),
reg_clk_vertices_(new VertexSet(graph_))
{
// For the benifit of reg_clk_vertices_ that references graph_.
graph_ = this;
}

Graph::~Graph()
{
delete vertices_;
delete edges_;
delete reg_clk_vertices_;
deleteSlewTables();
deleteArcDelayTables();
removeWidthCheckAnnotations();
Expand Down Expand Up @@ -396,7 +400,7 @@ Graph::makeVertex(Pin *pin,
vertex->init(pin, is_bidirect_drvr, is_reg_clk);
makeVertexSlews(vertex);
if (is_reg_clk)
reg_clk_vertices_.insert(vertex);
reg_clk_vertices_->insert(vertex);
return vertex;
}

Expand Down Expand Up @@ -432,7 +436,7 @@ void
Graph::deleteVertex(Vertex *vertex)
{
if (vertex->isRegClk())
reg_clk_vertices_.erase(vertex);
reg_clk_vertices_->erase(vertex);
Pin *pin = vertex->pin_;
if (vertex->isBidirectDriver())
pin_bidirect_drvr_vertex_map_.erase(pin_bidirect_drvr_vertex_map_
Expand Down Expand Up @@ -1599,4 +1603,23 @@ EdgesThruHierPinIterator::EdgesThruHierPinIterator(const Pin *hpin,
edge_iter_.init(edges_);
}

////////////////////////////////////////////////////////////////

VertexIdLess::VertexIdLess(Graph *&graph) :
graph_(graph)
{
}

bool
VertexIdLess::operator()(const Vertex *vertex1,
const Vertex *vertex2) const
{
return graph_->id(vertex1) < graph_->id(vertex2);
}

VertexSet::VertexSet(Graph *&graph) :
Set<Vertex*, VertexIdLess>(VertexIdLess(graph))
{
}

} // namespace
22 changes: 20 additions & 2 deletions include/sta/Graph.hh
Original file line number Diff line number Diff line change
Expand Up @@ -199,7 +199,7 @@ public:
float period);
// Remove all delay and slew annotations.
void removeDelaySlewAnnotations();
VertexSet *regClkVertices() { return &reg_clk_vertices_; }
VertexSet *regClkVertices() { return reg_clk_vertices_; }

static const int vertex_level_bits = 24;
static const int vertex_level_max = (1<<vertex_level_bits)-1;
Expand Down Expand Up @@ -261,7 +261,7 @@ protected:
// Sdf period check annotations.
PeriodCheckAnnotations *period_check_annotations_;
// Register/latch clock vertices to search from.
VertexSet reg_clk_vertices_;
VertexSet *reg_clk_vertices_;

friend class Vertex;
friend class VertexIterator;
Expand Down Expand Up @@ -526,4 +526,22 @@ private:
EdgeSet::Iterator edge_iter_;
};

class VertexIdLess
{
public:
VertexIdLess(Graph *&graph);
bool operator()(const Vertex *vertex1,
const Vertex *vertex2) const;

private:
Graph *&graph_;
};

class VertexSet : public Set<Vertex*, VertexIdLess>
{
public:
VertexSet(Graph *&graph);
VertexSet(const VertexSet &set);
};

} // namespace
2 changes: 1 addition & 1 deletion include/sta/GraphClass.hh
Original file line number Diff line number Diff line change
Expand Up @@ -32,11 +32,11 @@ class VertexIterator;
class VertexInEdgeIterator;
class VertexOutEdgeIterator;
class GraphLoop;
class VertexSet;

typedef ObjectId VertexId;
typedef ObjectId EdgeId;
typedef ObjectId ArcId;
typedef Set<Vertex*> VertexSet;
typedef Vector<Vertex*> VertexSeq;
typedef Vector<Edge*> EdgeSeq;
typedef Set<Edge*> EdgeSet;
Expand Down
8 changes: 4 additions & 4 deletions include/sta/Search.hh
Original file line number Diff line number Diff line change
Expand Up @@ -548,15 +548,15 @@ protected:
// Requireds have been seeded by searching arrivals to all endpoints.
bool requireds_seeded_;
// Vertices with invalid arrival times to update and search from.
VertexSet invalid_arrivals_;
VertexSet *invalid_arrivals_;
std::mutex invalid_arrivals_lock_;
BfsFwdIterator *arrival_iter_;
// Vertices with invalid required times to update and search from.
VertexSet invalid_requireds_;
VertexSet *invalid_requireds_;
BfsBkwdIterator *required_iter_;
bool tns_exists_;
// Endpoint vertices with slacks that have changed since tns was found.
VertexSet invalid_tns_;
VertexSet *invalid_tns_;
// Indexed by path_ap->index().
SlackSeq tns_;
// Indexed by path_ap->index().
Expand Down Expand Up @@ -585,7 +585,7 @@ protected:
TagGroupIndex tag_group_capacity_;
std::mutex tag_group_lock_;
// Latches data outputs to queue on the next search pass.
VertexSet pending_latch_outputs_;
VertexSet *pending_latch_outputs_;
std::mutex pending_latch_outputs_lock_;
VertexSet *endpoints_;
VertexSet *invalid_endpoints_;
Expand Down
2 changes: 2 additions & 0 deletions include/sta/Sta.hh
Original file line number Diff line number Diff line change
Expand Up @@ -984,6 +984,8 @@ public:
Arrival vertexArrival(Vertex *vertex,
const RiseFall *rf,
const PathAnalysisPt *path_ap);
Arrival vertexArrival(Vertex *vertex,
const MinMax *min_max);
Required vertexRequired(Vertex *vertex,
const MinMax *min_max);
Required vertexRequired(Vertex *vertex,
Expand Down
6 changes: 2 additions & 4 deletions search/CheckTiming.cc
Original file line number Diff line number Diff line change
Expand Up @@ -153,9 +153,7 @@ CheckTiming::checkRegClks(bool reg_multiple_clks,
bool reg_no_clks)
{
PinSet no_clk_pins, multiple_clk_pins;
VertexSet::ConstIterator reg_clk_iter(graph_->regClkVertices());
while (reg_clk_iter.hasNext()) {
Vertex *vertex = reg_clk_iter.next();
for (Vertex *vertex : *graph_->regClkVertices()) {
Pin *pin = vertex->pin();
ClockSet clks;
search_->clocks(vertex, clks);
Expand Down Expand Up @@ -318,7 +316,7 @@ CheckTiming::checkGeneratedClocks()
if (clk->isGenerated()) {
search_->genclks()->checkMaster(clk);
bool found_clk = false;
VertexSet src_vertices;
VertexSet src_vertices(graph_);
clk->srcPinVertices(src_vertices, network_, graph_);
VertexSet::Iterator vertex_iter(src_vertices);
while (vertex_iter.hasNext()) {
Expand Down
6 changes: 2 additions & 4 deletions search/ClkSkew.cc
Original file line number Diff line number Diff line change
Expand Up @@ -190,9 +190,7 @@ ClkSkews::findClkSkew(ClockSet *clks,
const SetupHold *setup_hold,
ClkSkewMap &skews)
{
VertexSet::ConstIterator reg_clk_iter(graph_->regClkVertices());
while (reg_clk_iter.hasNext()) {
Vertex *src_vertex = reg_clk_iter.next();
for (Vertex *src_vertex : *graph_->regClkVertices()) {
if (hasClkPaths(src_vertex, clks)) {
VertexOutEdgeIterator edge_iter(src_vertex, graph_);
while (edge_iter.hasNext()) {
Expand Down Expand Up @@ -343,7 +341,7 @@ ClkSkews::findFanout(Vertex *from)
{
debugPrint(debug_, "fanout", 1, "%s",
from->name(sdc_network_));
VertexSet endpoints;
VertexSet endpoints(graph_);
FanOutSrchPred pred(this);
BfsFwdIterator fanout_iter(BfsIndex::other, &pred, this);
fanout_iter.enqueue(from);
Expand Down
6 changes: 2 additions & 4 deletions search/FindRegister.cc
Original file line number Diff line number Diff line change
Expand Up @@ -139,7 +139,7 @@ FindRegVisitor::visitRegs(ClockSet *clks,
while (clk_iter.hasNext()) {
Clock *clk = clk_iter.next();
FindRegClkPred clk_pred(clk, this);
VertexSet visited_vertices;
VertexSet visited_vertices(graph_);
for (Pin *pin : clk->leafPins()) {
Vertex *vertex, *bidirect_drvr_vertex;
graph_->pinVertices(pin, vertex, bidirect_drvr_vertex);
Expand All @@ -158,9 +158,7 @@ FindRegVisitor::visitRegs(ClockSet *clks,
}
}
else {
VertexSet::ConstIterator reg_clk_iter(graph_->regClkVertices());
while (reg_clk_iter.hasNext()) {
Vertex *vertex = reg_clk_iter.next();
for (Vertex *vertex : *graph_->regClkVertices()) {
visitRegs(vertex->pin(), TimingSense::positive_unate,
RiseFallBoth::riseFall(),
edge_triggered, latches);
Expand Down
8 changes: 4 additions & 4 deletions search/Genclks.cc
Original file line number Diff line number Diff line change
Expand Up @@ -389,7 +389,7 @@ void
Genclks::seedSrcPins(Clock *clk,
BfsBkwdIterator &iter)
{
VertexSet src_vertices;
VertexSet src_vertices(graph_);
clk->srcPinVertices(src_vertices, network_, graph_);
VertexSet::Iterator vertex_iter(src_vertices);
while (vertex_iter.hasNext()) {
Expand Down Expand Up @@ -583,7 +583,7 @@ Genclks::makeGenclkInfo(Clock *gclk)
{
FilterPath *src_filter = makeSrcFilter(gclk);
Level gclk_level = clkPinMaxLevel(gclk);
VertexSet *fanins = new VertexSet;
VertexSet *fanins = new VertexSet(graph_);
findFanin(gclk, fanins);
GenclkInfo *genclk_info = new GenclkInfo(gclk, gclk_level, fanins,
src_filter);
Expand Down Expand Up @@ -643,8 +643,8 @@ Genclks::findLatchFdbkEdges(const Clock *gclk,
EdgeSet *fdbk_edges = nullptr;
for (Pin *pin : gclk->masterClk()->leafPins()) {
Vertex *vertex = graph_->pinDrvrVertex(pin);
VertexSet path_vertices;
VertexSet visited_vertices;
VertexSet path_vertices(graph_);
VertexSet visited_vertices(graph_);
SearchPred1 srch_pred(this);
findLatchFdbkEdges(vertex, gclk_level, srch_pred, path_vertices,
visited_vertices, fdbk_edges);
Expand Down
Loading

0 comments on commit 61c0f9d

Please sign in to comment.