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Rename zeroriscy to ibex
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This commit was prepared by the following script, followed by manual
fixes as needed.

```sh
sed -e 's/zeroriscy/ibex/g' -i.bak *.sv *.md *.yml
sed -e 's/zero-riscy/ibex/g' -i.bak *.sv *.md *.yml
sed -e 's/zeroriscy/ibex/g' -i.bak include/*.sv
sed -e 's/zero-riscy/ibex/g' -i.bak include/*.sv
sed -e 's/cluster_clock_gating/clock_gating/g' -i.bak *.sv
rm -f *.bak
rm -f include/*.bak

find . -name 'zeroriscy_*' -exec bash -c 'file={}; git mv $file ${file/zeroriscy/ibex}' \;
```
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@imphil
Eunchan Kim authored and imphil committed Apr 26, 2019
1 parent b1b89f5 commit 3a42f12
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Showing 24 changed files with 130 additions and 130 deletions.
10 changes: 5 additions & 5 deletions README.md
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@@ -1,10 +1,10 @@
# zero-riscy: RISC-V Core
# ibex: RISC-V Core

*zero-riscy** is a small 2-stage RISC-V core derived from RI5CY.
**ibex** is a small 2-stage RISC-V core derived from RI5CY.

**zero-riscy** fully implements the RV32IMC instruction set and a minimal
**ibex** fully implements the RV32IMC instruction set and a minimal
set of RISCV privileged specifications.
**zero-riscy** can be configured to be very small by disabling the RV32M extensions
**ibex** can be configured to be very small by disabling the RV32M extensions
and by activating the RV32E extensions. This configuration is called **micro-riscy**

The core was developed as part of the [PULP platform](http://pulp.ethz.ch/) for
Expand All @@ -14,5 +14,5 @@ PULP and PULPino.
## Documentation

A datasheet that explains the most important features of the core can be found
in the doc folder.
in the doc folder.

8 changes: 4 additions & 4 deletions zeroriscy_alu.sv → ibex_alu.sv
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Expand Up @@ -16,18 +16,18 @@
// Davide Schiavone - [email protected] //
// //
// Design Name: ALU //
// Project Name: zero-riscy //
// Project Name: ibex //
// Language: SystemVerilog //
// //
// Description: Arithmetic logic unit of the pipelined processor. //
// //
////////////////////////////////////////////////////////////////////////////////

`include "zeroriscy_config.sv"
`include "ibex_config.sv"

import zeroriscy_defines::*;
import ibex_defines::*;

module zeroriscy_alu
module ibex_alu
(
input logic [ALU_OP_WIDTH-1:0] operator_i,
input logic [31:0] operand_a_i,
Expand Down
6 changes: 3 additions & 3 deletions zeroriscy_compressed_decoder.sv → ibex_compressed_decoder.sv
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Expand Up @@ -13,7 +13,7 @@
// Engineer: Sven Stucki - [email protected] //
// //
// Design Name: Compressed instruction decoder //
// Project Name: zero-riscy //
// Project Name: ibex //
// Language: SystemVerilog //
// //
// Description: Decodes RISC-V compressed instructions into their RV32 //
Expand All @@ -22,9 +22,9 @@
////////////////////////////////////////////////////////////////////////////////


import zeroriscy_defines::*;
import ibex_defines::*;

module zeroriscy_compressed_decoder
module ibex_compressed_decoder
(
input logic [31:0] instr_i,
output logic [31:0] instr_o,
Expand Down
12 changes: 6 additions & 6 deletions zeroriscy_controller.sv → ibex_controller.sv
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Expand Up @@ -18,19 +18,19 @@
// Davide Schiavone - [email protected] //
// //
// Design Name: Main controller //
// Project Name: zero-riscy //
// Project Name: ibex //
// Language: SystemVerilog //
// //
// Description: Main CPU controller of the processor //
// //
////////////////////////////////////////////////////////////////////////////////

`include "zeroriscy_config.sv"
`include "ibex_config.sv"

import zeroriscy_defines::*;
import ibex_defines::*;


module zeroriscy_controller
module ibex_controller
#(
parameter REG_ADDR_WIDTH = 5
)
Expand Down Expand Up @@ -134,8 +134,8 @@ module zeroriscy_controller
begin
// print warning in case of decoding errors
if (is_decoding_o && illegal_insn_i) begin
$display("%t: Illegal instruction (core %0d) at PC 0x%h:", $time, zeroriscy_core.core_id_i,
zeroriscy_id_stage.pc_id_i);
$display("%t: Illegal instruction (core %0d) at PC 0x%h:", $time, ibex_core.core_id_i,
ibex_id_stage.pc_id_i);
end
end
// synopsys translate_on
Expand Down
24 changes: 12 additions & 12 deletions zeroriscy_core.sv → ibex_core.sv
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Expand Up @@ -19,18 +19,18 @@
// Davide Schiavone - [email protected] //
// //
// Design Name: Top level module //
// Project Name: zero-riscy //
// Project Name: ibex //
// Language: SystemVerilog //
// //
// Description: Top level module of the RISC-V core. //
// //
////////////////////////////////////////////////////////////////////////////////

`include "zeroriscy_config.sv"
`include "ibex_config.sv"

import zeroriscy_defines::*;
import ibex_defines::*;

module zeroriscy_core
module ibex_core
#(
parameter N_EXT_PERF_COUNTERS = 0,
parameter RV32E = 0,
Expand Down Expand Up @@ -266,7 +266,7 @@ module zeroriscy_core
// main clock gate of the core
// generates all clocks except the one for the debug unit which is
// independent
cluster_clock_gating core_clock_gate_i
clock_gating core_clock_gate_i
(
.clk_i ( clk_i ),
.en_i ( clock_en ),
Expand All @@ -282,7 +282,7 @@ module zeroriscy_core
// |___|_| |____/ |_/_/ \_\____|_____| //
// //
//////////////////////////////////////////////////
zeroriscy_if_stage if_stage_i
ibex_if_stage if_stage_i
(
.clk ( clk ),
.rst_n ( rst_ni ),
Expand Down Expand Up @@ -341,7 +341,7 @@ module zeroriscy_core
// |___|____/ |____/ |_/_/ \_\____|_____| //
// //
/////////////////////////////////////////////////
zeroriscy_id_stage
ibex_id_stage
#(
.RV32E(RV32E),
.RV32M(RV32M)
Expand Down Expand Up @@ -459,7 +459,7 @@ module zeroriscy_core
);


zeroriscy_ex_block
ibex_ex_block
#(
//change the localparam MULT_TYPE to 0 or 1
//if you want a SLOW or FAST multiplier
Expand Down Expand Up @@ -503,7 +503,7 @@ module zeroriscy_core
// //
////////////////////////////////////////////////////////////////////////////////////////

zeroriscy_load_store_unit load_store_unit_i
ibex_load_store_unit load_store_unit_i
(
.clk ( clk ),
.rst_n ( rst_ni ),
Expand Down Expand Up @@ -556,7 +556,7 @@ module zeroriscy_core
// Control and Status Registers //
//////////////////////////////////////

zeroriscy_cs_registers
ibex_cs_registers
#(
.N_EXT_CNT ( N_EXT_PERF_COUNTERS )
)
Expand Down Expand Up @@ -627,7 +627,7 @@ module zeroriscy_core
// //
/////////////////////////////////////////////////////////////

zeroriscy_debug_unit debug_unit_i
ibex_debug_unit debug_unit_i
(
.clk ( clk_i ), // always-running clock for debug
.rst_n ( rst_ni ),
Expand Down Expand Up @@ -682,7 +682,7 @@ module zeroriscy_core

`ifndef VERILATOR
`ifdef TRACE_EXECUTION
zeroriscy_tracer zeroriscy_tracer_i
ibex_tracer ibex_tracer_i
(
.clk ( clk_i ), // always-running clock for tracing
.rst_n ( rst_ni ),
Expand Down
8 changes: 4 additions & 4 deletions zeroriscy_cs_registers.sv → ibex_cs_registers.sv
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Expand Up @@ -16,25 +16,25 @@
// Davide Schiavone - [email protected] //
// //
// Design Name: Control and Status Registers //
// Project Name: zero-riscy //
// Project Name: ibex //
// Language: SystemVerilog //
// //
// Description: Control and Status Registers (CSRs) loosely following the //
// RiscV draft priviledged instruction set spec (v1.9) //
// //
////////////////////////////////////////////////////////////////////////////////

`include "zeroriscy_config.sv"
`include "ibex_config.sv"

import zeroriscy_defines::*;
import ibex_defines::*;

`ifndef PULP_FPGA_EMUL
`ifdef SYNTHESIS
`define ASIC_SYNTHESIS
`endif
`endif

module zeroriscy_cs_registers
module ibex_cs_registers
#(
parameter N_EXT_CNT = 0
)
Expand Down
8 changes: 4 additions & 4 deletions zeroriscy_debug_unit.sv → ibex_debug_unit.sv
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Expand Up @@ -15,18 +15,18 @@
// Davide Schiavone - [email protected] //
// //
// Design Name: Debug Unit //
// Project Name: zero-riscy //
// Project Name: ibex //
// Language: SystemVerilog //
// //
// Description: Debug controller //
// //
////////////////////////////////////////////////////////////////////////////////

`include "zeroriscy_config.sv"
`include "ibex_config.sv"

import zeroriscy_defines::*;
import ibex_defines::*;

module zeroriscy_debug_unit
module ibex_debug_unit
#(
parameter REG_ADDR_WIDTH = 5
)
Expand Down
8 changes: 4 additions & 4 deletions zeroriscy_decoder.sv → ibex_decoder.sv
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Expand Up @@ -19,18 +19,18 @@
// Markus Wegmann - [email protected] //
// //
// Design Name: Decoder //
// Project Name: zero-riscy //
// Project Name: ibex //
// Language: SystemVerilog //
// //
// Description: Decoder //
// //
////////////////////////////////////////////////////////////////////////////////

`include "zeroriscy_config.sv"
`include "ibex_config.sv"

import zeroriscy_defines::*;
import ibex_defines::*;

module zeroriscy_decoder
module ibex_decoder
#(
parameter RV32M = 1
)
Expand Down
14 changes: 7 additions & 7 deletions zeroriscy_ex_block.sv → ibex_ex_block.sv
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Expand Up @@ -19,18 +19,18 @@
// Davide Schiavone - [email protected] //
// //
// Design Name: Execute stage //
// Project Name: zero-riscy //
// Project Name: ibex //
// Language: SystemVerilog //
// //
// Description: Execution block: Hosts ALU and MUL/DIV unit //
// //
////////////////////////////////////////////////////////////////////////////////

`include "zeroriscy_config.sv"
`include "ibex_config.sv"

import zeroriscy_defines::*;
import ibex_defines::*;

module zeroriscy_ex_block
module ibex_ex_block
#(
parameter RV32M = 1
)
Expand Down Expand Up @@ -106,7 +106,7 @@ endgenerate
// //
////////////////////////////

zeroriscy_alu alu_i
ibex_alu alu_i
(
.operator_i ( alu_operator_i ),
.operand_a_i ( alu_operand_a_i ),
Expand All @@ -132,7 +132,7 @@ endgenerate

generate
if (MULT_TYPE == 0) begin : multdiv_slow
zeroriscy_multdiv_slow multdiv_i
ibex_multdiv_slow multdiv_i
(
.clk ( clk ),
.rst_n ( rst_n ),
Expand All @@ -151,7 +151,7 @@ endgenerate
.multdiv_result_o ( multdiv_result )
);
end else begin: multdiv_fast
zeroriscy_multdiv_fast multdiv_i
ibex_multdiv_fast multdiv_i
(
.clk ( clk ),
.rst_n ( rst_n ),
Expand Down
6 changes: 3 additions & 3 deletions zeroriscy_fetch_fifo.sv → ibex_fetch_fifo.sv
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Expand Up @@ -12,18 +12,18 @@
// Engineer: Andreas Traber - [email protected] //
// //
// Design Name: Fetch Fifo for 32 bit memory interface //
// Project Name: zero-riscy //
// Project Name: ibex //
// Language: SystemVerilog //
// //
// Description: Fetch fifo //
////////////////////////////////////////////////////////////////////////////////

`include "zeroriscy_config.sv"
`include "ibex_config.sv"

// input port: send address one cycle before the data
// clear_i clears the FIFO for the following cycle. in_addr_i can be sent in
// this cycle already
module zeroriscy_fetch_fifo
module ibex_fetch_fifo
(
input logic clk,
input logic rst_n,
Expand Down
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