Update sys, support for more games.

MiSTer-devel · Feb 19, 2020 · a71ff10 · a71ff10
1 parent fae0b74
commit a71ff10
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Showing 25 changed files with 890 additions and 3,537 deletions.
diff --git a/Arcade-Defender.srf b/Arcade-Defender.srf
@@ -13,6 +13,7 @@
 { "" "" "" "Port \"reset_value\" on the entity instantiation of \"h_counter\" is connected to a signal of width 32. The formal width of the signal in the module is 16.  The extra bits will be ignored." {  } {  } 0 12020 "" 0 0 "Design Software" 0 -1 0 ""}
 { "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" {  } {  } 0 332043 "" 0 0 "Design Software" 0 -1 0 ""}
 { "" "" "" "LOCKED port on the PLL is not properly connected on instance \"emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." {  } {  } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "*" {  } {  } 0 276027 "" 0 0 "Design Software" 0 -1 0 ""}
 { "" "" "" "Vip.vip: Module dependency loop involving: \"HPS\"" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
 { "" "" "" "alt_vip_common_frame_counter.v" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
 { "" "" "" "alt_vip_cvo_mode_banks.sv" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}