icache: support data/tag r/w op (OpenXiangShan#1337)

* mem,cacheop: fix read data writeback

* mem,cacheop: rename cacheop state bits

These bits are different from w_*, s_* bits in cache

* mem: enable icache op feedback

* icache: update cache op implementation

* chore: remove cache op logic from XSCore.scala

src/main/scala/xiangshan/XSCore.scala

@@ -364,7 +364,10 @@ class XSCoreImp(outer: XSCoreBase) extends LazyModuleImp(outer)
   csrioIn.externalInterrupt.seip := outer.plic_int_sink.in.last._1(0)
   csrioIn.externalInterrupt.debug := outer.debug_int_sink.in.head._1(0)
 
-  csrioIn.distributedUpdate <> memBlock.io.csrUpdate // TODO
+  csrioIn.distributedUpdate(0).w.valid := memBlock.io.csrUpdate.w.valid
+  csrioIn.distributedUpdate(0).w.bits := memBlock.io.csrUpdate.w.bits
+  csrioIn.distributedUpdate(1).w.valid := frontend.io.csrUpdate.w.valid
+  csrioIn.distributedUpdate(1).w.bits := frontend.io.csrUpdate.w.bits
 
   fenceio.sfence <> memBlock.io.sfence
   fenceio.sbuffer <> memBlock.io.fenceToSbuffer

src/main/scala/xiangshan/backend/MemBlock.scala

@@ -100,7 +100,7 @@ class MemBlockImp(outer: MemBlock) extends LazyModuleImp(outer)
   val uncache = outer.uncache.module
 
   dcache.io.csr.distribute_csr <> io.csrCtrl.distribute_csr
-  io.csrUpdate <> dcache.io.csr.update
+  io.csrUpdate := RegNext(dcache.io.csr.update)
   io.error <> RegNext(RegNext(dcache.io.error))
 
   val loadUnits = Seq.fill(exuParameters.LduCnt)(Module(new LoadUnit))

src/main/scala/xiangshan/backend/fu/CSR.scala

@@ -120,7 +120,7 @@ class CSRFileIO(implicit p: Parameters) extends XSBundle {
   // Custom microarchiture ctrl signal
   val customCtrl = Output(new CustomCSRCtrlIO)
   // distributed csr write
-  val distributedUpdate = Flipped(new DistributedCSRUpdateReq)
+  val distributedUpdate = Vec(2, Flipped(new DistributedCSRUpdateReq))
 }
 
 class CSR(implicit p: Parameters) extends FunctionUnit with HasCSRConst with PMPMethod with PMAMethod with HasTriggerConst
@@ -1052,12 +1052,27 @@ class CSR(implicit p: Parameters) extends FunctionUnit with HasCSRConst with PMP
   // Distributed CSR update req
   //
   // For now we use it to implement customized cache op
+  // It can be delayed if necessary
+
+  val delayedUpdate0 = DelayN(csrio.distributedUpdate(0), 2)
+  val delayedUpdate1 = DelayN(csrio.distributedUpdate(1), 2)
+  val distributedUpdateValid = delayedUpdate0.w.valid || delayedUpdate1.w.valid
+  val distributedUpdateAddr = Mux(delayedUpdate0.w.valid, 
+    delayedUpdate0.w.bits.addr,
+    delayedUpdate1.w.bits.addr
+  )
+  val distributedUpdateData = Mux(delayedUpdate0.w.valid, 
+    delayedUpdate0.w.bits.data,
+    delayedUpdate1.w.bits.data
+  )
+
+  assert(!(delayedUpdate0.w.valid && delayedUpdate1.w.valid))
 
-  when(csrio.distributedUpdate.w.valid){
+  when(distributedUpdateValid){
     // cacheopRegs can be distributed updated
     CacheInstrucion.CacheInsRegisterList.map{case (name, attribute) => {
-      when((Scachebase + attribute("offset").toInt).U === csrio.distributedUpdate.w.bits.addr){
-        cacheopRegs(name) := csrio.distributedUpdate.w.bits.data
+      when((Scachebase + attribute("offset").toInt).U === distributedUpdateAddr){
+        cacheopRegs(name) := distributedUpdateData
       }
     }}
   }

src/main/scala/xiangshan/frontend/Frontend.scala

@@ -113,7 +113,7 @@ class FrontendImp (outer: Frontend) extends LazyModuleImp(outer)
   //icache.io.missQueue.flush := ifu.io.ftqInter.fromFtq.redirect.valid || (ifu.io.ftqInter.toFtq.pdWb.valid && ifu.io.ftqInter.toFtq.pdWb.bits.misOffset.valid)
 
   icache.io.csr.distribute_csr <> io.csrCtrl.distribute_csr
-  icache.io.csr.update <> io.csrUpdate
+  io.csrUpdate := RegNext(icache.io.csr.update)
 
   //IFU-Ibuffer
   ifu.io.toIbuffer    <> ibuffer.io.in

src/main/scala/xiangshan/frontend/icache/ICache.scala

@@ -306,8 +306,8 @@ class ICacheDataArray(implicit p: Parameters) extends ICacheArray
   val bank_0_idx = Mux(port_0_read_0, io.read.bits.vSetIdx(0), io.read.bits.vSetIdx(1))
   val bank_1_idx = Mux(port_0_read_1, io.read.bits.vSetIdx(0), io.read.bits.vSetIdx(1))
 
-  val write_bank_0 = io.write.valid && !io.write.bits.bankIdx
-  val write_bank_1 = io.write.valid &&  io.write.bits.bankIdx
+  val write_bank_0 = WireInit(io.write.valid && !io.write.bits.bankIdx)
+  val write_bank_1 = WireInit(io.write.valid &&  io.write.bits.bankIdx)
 
   val write_data_bits = Wire(UInt(dataEntryBits.W))
 
@@ -350,7 +350,7 @@ class ICacheDataArray(implicit p: Parameters) extends ICacheArray
 
   //Parity Encode
   val write = io.write.bits
-  val write_data = write.data.asTypeOf(Vec(dataUnitNum, UInt(dataCodeUnit.W)))
+  val write_data = WireInit(write.data.asTypeOf(Vec(dataUnitNum, UInt(dataCodeUnit.W))))
   val write_data_encoded = VecInit(write_data.map( unit_bits => cacheParams.dataCode.encode(unit_bits) ))
   write_data_bits := write_data_encoded.asUInt
 
@@ -377,31 +377,20 @@ class ICacheDataArray(implicit p: Parameters) extends ICacheArray
     when(CacheInstrucion.isWriteData(io.cacheOp.req.bits.opCode)){
       (0 until 2).map(i => {
         dataArrays(i).io.w.req.valid := io.cacheOp.req.bits.bank_num === i.U
-        dataArrays(i).io.w.req.bits.apply(
-          data = io.cacheOp.req.bits.write_data_vec.asUInt,
-          setIdx = io.cacheOp.req.bits.index,
-          waymask = UIntToOH(io.cacheOp.req.bits.wayNum(4, 0))
-        )
+        dataArrays(i).io.w.req.bits.setIdx := io.cacheOp.req.bits.index
+        dataArrays(i).io.w.req.bits.waymask match {
+          case Some(waymask) => waymask := UIntToOH(io.cacheOp.req.bits.wayNum(4, 0))
+          case None =>
+        }
       })
+      write_data := io.cacheOp.req.bits.write_data_vec.asTypeOf(write_data.cloneType)
       cacheOpShouldResp := true.B
     }
-    // when(CacheInstrucion.isWriteDataECC(io.cacheOp.req.bits.opCode)){
-    //   for (bank_index <- 0 until DCacheBanks) {
-    //     val ecc_bank = ecc_banks(bank_index)
-    //     ecc_bank.io.w.req.valid := true.B
-    //     ecc_bank.io.w.req.bits.apply(
-    //       setIdx = io.cacheOp.req.bits.index,
-    //       data = io.cacheOp.req.bits.write_data_ecc,
-    //       waymask = UIntToOH(io.cacheOp.req.bits.wayNum(4, 0))
-    //     )
-    //   }
-    //   cacheOpShouldResp := true.B
-    // }
   }
   io.cacheOp.resp.valid := RegNext(io.cacheOp.req.valid && cacheOpShouldResp)
   val dataresp = Mux(io.cacheOp.req.bits.bank_num(0).asBool,
-    dataArrays(0).io.r.resp.data.asTypeOf(Vec(nWays, UInt(blockBits.W))),
-    dataArrays(1).io.r.resp.data.asTypeOf(Vec(nWays, UInt(blockBits.W)))
+    read_datas(1),
+    read_datas(0)
   )
 
   val numICacheLineWords = blockBits / 64