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Commits on Dec 17, 2021

• pmp: add static pmp check that stored in tlb entries (OpenXiangShan#1366)

  Show description for 5b7ef04
  Lemover

  authored
  5b7ef04

• csr: use zext pc when vm is disabled (OpenXiangShan#1361)

  poemonsense

  authored
  bd1f1bf

• Change default L3 size to 6MB (OpenXiangShan#1365)

  Show description for 0fbed46
  ljwljwljwljw

  authored
  0fbed46

Commits on Dec 16, 2021

• rename: check valid condition for lui (OpenXiangShan#1368)

  poemonsense

  authored
  89c0fb0

• dcache: remove redundant ecc array (OpenXiangShan#1358)

  Show description for 77decb4
  

  zhanglinjuan

  authored
  77decb4

• Fix false hit bug after IFU timing optimization (OpenXiangShan#1367)

  Show description for a1351e5
  

  jinyue110

  and

  poemonsense

  authored
  a1351e5

Commits on Dec 15, 2021

• Debug Mode: support difftest with spike (OpenXiangShan#1363)

  Show description for f1c56d6
  notlqr

  authored
  f1c56d6

• mem: writeback atom exception from store wb port 0 (OpenXiangShan#1353)

  AugustusWillisWang

  authored
  858c53d

• mmpma: fix mmpma's read/write decoupled logic (OpenXiangShan#1354)

  Show description for cef5c4b
  Lemover

  authored
  cef5c4b

• rename: add fused lui and load (OpenXiangShan#1356)

  Show description for fd7603d
  poemonsense

  authored
  fd7603d

Commits on Dec 14, 2021

• README: fix a typo (OpenXiangShan#1357)

  Tang-Haojin

  authored
  6a326a7

• difftest: move sc_valid to AtomicsUnit (OpenXiangShan#1350)

  poemonsense

  authored
  e13d224

• dp2: out.bits does not depend on lsq.canAccept (OpenXiangShan#1352)

  Show description for 74ca315
  poemonsense

  authored
  74ca315

• Optimize IFU and PreDecode timing (OpenXiangShan#1347)

  Show description for 2a3050c
  jinyue110

  authored
  2a3050c

• dcache: fix bug in ecc check (OpenXiangShan#1349)

  linjuanZ

  authored
  dd95524

• csr: update mtval/stval according to the trap mode (OpenXiangShan#1344)

  Show description for 7c07165
  poemonsense

  authored
  7c07165

Commits on Dec 13, 2021

• Optimize dcache timing (OpenXiangShan#1332)

  Show description for 6979007
  

  linjuanZ

  and

  AugustusWillisWang

  authored
  6979007

• Merge pull request OpenXiangShan#1345 from OpenXiangShan/fix-soft-prefetch

  Show description for 979fa9b
  poemonsense

  authored
  979fa9b

• SoC: insert more buffers into mmio path (OpenXiangShan#1329)

  Show description for be340b1
  

  4 peopleauthored
  be340b1

Commits on Dec 12, 2021

• mem: replay soft prefetch if tlb miss

  AugustusWillisWang

  committed
  c707f0c

• L2/L3: fix prefetch train address (OpenXiangShan#1339)

  Show description for 459ad1b
  ljwljwljwljw

  authored
  459ad1b

• csr: add soft_prefetch_enable to smblockctl

  AugustusWillisWang

  committed
  d10a581

• mem: soft prefetch will not be replayed

  Show description for 690158b
  AugustusWillisWang

  committed
  690158b

• csr: add vectored trap mode (OpenXiangShan#1343)

  Show description for 68b89fc
  poemonsense

  authored
  68b89fc

Commits on Dec 11, 2021

• jump: set the LSB of the target to zero (OpenXiangShan#1342)

  Show description for 1a389df
  poemonsense

  authored
  1a389df

• csr: delay fflags and dirty_fs for better timing (OpenXiangShan#1341)

  poemonsense

  authored
  7181c0c

• mmu: timing optimization of ptwfilter's recv and issue & storeunit's mmio (OpenXiangShan#1326)

  Show description for 2c2c158
  Lemover

  authored
  2c2c158

• core: delay csrCtrl for two cycles (OpenXiangShan#1336)

  Show description for 6f688da
  poemonsense

  authored
  6f688da

Commits on Dec 10, 2021

• icache: support data/tag r/w op (OpenXiangShan#1337)

  Show description for 7089983
  AugustusWillisWang

  authored
  7089983

• dcache: fix lrsc_locked_block check (OpenXiangShan#1334)

  AugustusWillisWang

  authored
  8b538b5

• core: refactor hardware performance counters (OpenXiangShan#1335)

  Show description for 1ca0e4f
  poemonsense

  authored
  1ca0e4f

• bump huancun (OpenXiangShan#1322)

  Show description for 1dc3a3a
  

  wakafa1

  and

  ljwljwljwljw

  authored
  1dc3a3a

Commits on Dec 9, 2021

• ICache: send ProbeAck when Probe NToN (OpenXiangShan#1331)

  jinyue110

  authored
  1d4a76a

• core: refactor writeback parameters (OpenXiangShan#1327)

  Show description for 6ab6918
  poemonsense

  authored
  6ab6918

Commits on Dec 8, 2021

• csr: add write mask to satp.ppn & xstatus.xs (OpenXiangShan#1323)

  Show description for 705cbec
  Lemover

  authored
  705cbec

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