Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks

A neural network built in Verilog for the DE1-SoC FPGA board for handwritten digit recognition.

lowRISC Style Guides

A 2D convolution hardware implementation written in Verilog

Implementation of CNN on ZYNQ FPGA to classify handwritten numbers using MNIST database

Verilog Content Addressable Memory Module

My implementation of the RV32I core, along with some extensions to fit on Terasic's DE2 FPGA board.