TuShare is a utility for crawling historical data of China stocks

Biweekly Sync Meeting for RISC-V Software Ecosystem. Meeting time is more friendly for people living in East Asia.

Penalized Sparse Learning Solver - Unleash the Power of Nonconvex Penalty

A Fast, Low-Overhead On-chip Network

Implementation of basic ML algorithms from scratch in python...

Learning to create Machine Learning Algorithms

In this project we are comparing various regression models to find which model works better for predicting the AQI (Air Quality Index).

Official implementation code of the paper <AnyText: Multilingual Visual Text Generation And Editing>

시계열 데이터에 대한 예측 문제를 Pytorch로 구현한 레포입니다. RNN, LSTM, GRU, CNN과 같은 기본 모델부터 TCN, TFT, Transformer 기반의 최신 모델까지 동일 데이터에 대해 실험하고 정리하고자 합니다.

Time series forecasting with PyTorch

AeroSpace is an i3-like tiling window manager for macOS

A collection of inspiring lists, manuals, cheatsheets, blogs, hacks, one-liners, cli/web tools and more.

How I setup a Mac, with lots of productivity tools, step-by-step guide

分享 GitHub 上有趣、入门级的开源项目。Share interesting, entry-level open source projects on GitHub.

Course to get into Large Language Models (LLMs) with roadmaps and Colab notebooks.

Modern C++ Programming Course (C++03/11/14/17/20/23/26)

Crawl a site to generate knowledge files to create your own custom GPT from a URL

Modular hardware build system

An introductory series to Reinforcement Learning (RL) with comprehensive step-by-step tutorials.

GeST (Generating Stress-Tests) is a Genetic Algorithm framework for automatic hardware stress-test generation. Related scientific publication https://ieeexplore.ieee.org/document/8695639

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

经济学人(含音频)、纽约客、卫报、连线、大西洋月刊等英语杂志免费下载,支持epub、mobi、pdf格式, 每周更新

🦜🔗 Build context-aware reasoning applications

Scientific papers are coming out TOO DAMN FAST so we need a way to very quickly extract useful information.

FreeRTOS for PULP

Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools

Verilog UART

Linux capable RISC-V SoC designed to be readable and useful.

解锁完整的 Apple功能和集成服务

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog