VerilogUtilIP

The project has been moved here https://git.morgothdisk.com/explore/projects

Here is a bunch of util IPs

All IPs from this project are licensed under GPL license until othervice is specified.

Name		Name	Last commit message	Last commit date
Latest commit History 25 Commits
ddr		ddr
encryption_cores		encryption_cores
xmega_core		xmega_core
.gitattributes		.gitattributes
.gitignore		.gitignore
README.md		README.md
add_w_carry.v		add_w_carry.v
adder.v		adder.v
bin_to_bcd.v		bin_to_bcd.v
counters.v		counters.v
divider.v		divider.v
fft.v		fft.v
flipflop.v		flipflop.v
i2c.v		i2c.v
i2c_simulation.v		i2c_simulation.v
memory.v		memory.v
multiplyer.v		multiplyer.v
pmods.vh		pmods.vh
serdes.v		serdes.v
spi_master.v		spi_master.v
string.v		string.v
uart_implementation.v		uart_implementation.v
uart_rx.v		uart_rx.v
uart_simulation.v		uart_simulation.v
uart_tx.v		uart_tx.v
util.v		util.v