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SERV - The SErial RISC-V CPU

Verilog 1,467 193 Updated Dec 18, 2024

Open source tools for IC design

8 1 Updated Dec 12, 2024

Collect some CS textbooks for learning.

750 210 Updated Jan 3, 2025
Verilog 83 25 Updated Sep 2, 2023
SystemVerilog 60 9 Updated Aug 6, 2024

Pure python implementation of SNN

Python 1,058 286 Updated Jul 29, 2022

Technically-oriented PDF Collection (Papers, Specs, Decks, Manuals, etc)

HTML 7,897 1,549 Updated Jan 6, 2025

Official inference repo for FLUX.1 models

Python 19,248 1,360 Updated Dec 31, 2024

This repo provide an index of VLSI content creators and their materials

138 18 Updated Aug 21, 2024

This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, with a comparison between using an LC VCO and using a Ring VCO.

MATLAB 58 14 Updated Jun 12, 2023
Verilog 1,294 279 Updated Dec 26, 2024

A list of papers, docs, codes about model quantization. This repo is aimed to provide the info for model quantization research, we are continuously improving the project. Welcome to PR the works (p…

1,946 209 Updated Nov 1, 2024

Repository collecting papers about neuromorphic hardware, such as ASIC and FPGA implementations of SNNs and stuff.

150 15 Updated Nov 4, 2023

Exercises done from the book : Vaibbhav Taraate - Digital Design Techniques and Exercises_ A Practice Book for Digital Logic Design-Springer (2021)

Tcl 1 Updated Sep 18, 2024

Duelyst is a digital collectible card game and turn-based strategy hybrid, developed by Counterplay Games.

JavaScript 3,668 567 Updated Aug 5, 2024

Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.

Verilog 389 197 Updated Jan 29, 2023

📡 Using Software Designed Radio to transmit OFDM QPSK signals at 5 GHz

MATLAB 166 74 Updated Apr 7, 2018
Verilog 85 40 Updated Dec 23, 2016

Python implementation of H264

Python 51 14 Updated Nov 26, 2018

H264视频解码verilog实现

Verilog 79 38 Updated Aug 11, 2017

A hardware h264 video encoder written in VHDL. Designed to be synthesized into an FPGA. Initial testing is using Xilinx tools and FPGAs but it is not specific to Xilinx.

VHDL 286 67 Updated May 16, 2021

This is the base repo for our graduation project in AlexU 21

SystemVerilog 28 13 Updated Jul 26, 2021