[ibex] Add reset bypass controls

Signed-off-by: Timothy Chen <[email protected]>
NXP · Apr 21, 2021 · 33cca5e · 33cca5e
1 parent 6c04708
commit 33cca5e
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Showing 4 changed files with 20 additions and 5 deletions.
diff --git a/doc/02_user/integration.rst b/doc/02_user/integration.rst
@@ -36,6 +36,7 @@ Instantiation Template
       .clk_i          (),
       .rst_ni         (),
       .test_en_i      (),
+      .scan_rst_ni    (),
       .ram_cfg_i      (),
 
       // Configuration
@@ -160,7 +161,11 @@ Interfaces
 +-------------------------+-------------------------+-----+----------------------------------------+
 | ``rst_ni``              | 1                       | in  | Active-low asynchronous reset          |
 +-------------------------+-------------------------+-----+----------------------------------------+
-| ``test_en_i``           | 1                       | in  | Test input, enables clock              |
+| ``test_en_i``           | 1                       | in  | Test input, enables clock and allows   |
+|                         |                         |     | test control of reset.                 |
++-------------------------+-------------------------+-----+----------------------------------------+
+| ``scan_rst_ni``         | 1                       | in  | Test controlled reset.  If DFT not     |
+|                         |                         |     | used, tie off to 0.                    |
 +-------------------------+-------------------------+-----+----------------------------------------+
 | ``ram_cfg_i``           | 10                      | in  | RAM configuration inputs, routed to    |
 |                         |                         |     | the icache RAMs                        |

diff --git a/rtl/ibex_lockstep.sv b/rtl/ibex_lockstep.sv
@@ -88,7 +88,9 @@ module ibex_lockstep import ibex_pkg::*; #(
 
     output logic                         alert_minor_o,
     output logic                         alert_major_o,
-    input  logic                         core_busy_i
+    input  logic                         core_busy_i,
+    input  logic                         test_en_i,
+    input  logic                         scan_rst_ni
 );
 
   localparam int unsigned LockstepOffsetW = $clog2(LockstepOffset);
@@ -118,7 +120,7 @@ module ibex_lockstep import ibex_pkg::*; #(
     end
   end
 
-  assign rst_shadow_n = rst_shadow_set_q;
+  assign rst_shadow_n = test_en_i ? scan_rst_ni : rst_shadow_set_q;
 
   //////////////////
   // Input delays //

diff --git a/rtl/ibex_top.sv b/rtl/ibex_top.sv
@@ -106,7 +106,10 @@ module ibex_top #(
     input  logic                         fetch_enable_i,
     output logic                         alert_minor_o,
     output logic                         alert_major_o,
-    output logic                         core_sleep_o
+    output logic                         core_sleep_o,
+
+    // DFT bypass controls
+    input logic                          scan_rst_ni
 );
 
   import ibex_pkg::*;
@@ -716,7 +719,9 @@ module ibex_top #(
 
       .alert_minor_o     (lockstep_alert_minor_local),
       .alert_major_o     (lockstep_alert_major_local),
-      .core_busy_i       (core_busy_local)
+      .core_busy_i       (core_busy_local),
+      .test_en_i         (test_en_i),
+      .scan_rst_ni       (scan_rst_ni)
     );
 
     // Manually buffer the output signals.
@@ -733,6 +738,8 @@ module ibex_top #(
   end else begin : gen_no_lockstep
     assign lockstep_alert_major = 1'b0;
     assign lockstep_alert_minor = 1'b0;
+    logic unused_scan;
+    assign unused_scan = scan_rst_ni;
   end
 
   // TODO - need a config to reset all registers before the lockstep alert can be used

diff --git a/rtl/ibex_top_tracing.sv b/rtl/ibex_top_tracing.sv
@@ -132,6 +132,7 @@ module ibex_top_tracing #(
     .rst_ni,
 
     .test_en_i,
+    .scan_rst_ni('0),
     .ram_cfg_i,
 
     .hart_id_i,