32-bit Superscalar RISC-V CPU

SERV - The SErial RISC-V CPU

RISC-V CPU Core (RV32IM)

PicoRV32 - A Size-Optimized RISC-V CPU

Open-source high-performance RISC-V processor

axi-crossbar form ysyx open source SoC

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Verilog AXI components for FPGA implementation

一步一步写MIPS CPU

第一个CPU项目

学习AXI接口，以及xilinx DDR3 IP使用

An FPGA-based DDR1 controller. 基于FPGA的DDR1控制器，为低端FPGA嵌入式系统提供廉价、大容量的存储。

Opensource DDR3 Controller

A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs

🌊 一款 Material Design 风格的 Hexo 主题 / An elegant Material-Design theme for Hexo

A Wonderful Theme for Hexo.

AXI总线连接器

An AXI4 crossbar implementation in SystemVerilog

AXI Interconnect

一个卡片类拟态风格的Hexo主题

a theme for hexo

一款Material Design风格的hexo主题

A Pure Theme For Hexo

A white and simple Hexo theme, originated from a Farbox theme

一个简洁优雅的hexo主题 A simple and elegant theme for hexo.

🔥 A special Hexo theme focusing on pictures and images. Images tell stories, and Nexmoe makes them more vivid.

Hardware implementation of the SHA256 algorithm using AXI bus interconnect on the Xilinx Artix 7 (Basys 3 development board).