VeeR EH1 core

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

An open-source microcontroller system based on RISC-V

educational microarchitectures for risc-v isa

SonicBOOM: The Berkeley Out-of-Order Machine

Rocket Chip Generator

🌳 The next generation integrated development environment for processor design and verification. It has multi-hardware language support, open source IP management and easy-to-use rtl simulation tool…

IC design and development should be faster，simpler and more reliable

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

A FPGA friendly 32 bit RISC-V CPU implementation

A minimal GPU design in Verilog to learn how GPUs work from the ground up

32-bit Superscalar RISC-V CPU

SERV - The SErial RISC-V CPU

RISC-V CPU Core (RV32IM)

PicoRV32 - A Size-Optimized RISC-V CPU

Open-source high-performance RISC-V processor

axi-crossbar form ysyx open source SoC

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Verilog AXI components for FPGA implementation

一步一步写MIPS CPU

第一个CPU项目

学习AXI接口，以及xilinx DDR3 IP使用

An FPGA-based DDR1 controller. 基于FPGA的DDR1控制器，为低端FPGA嵌入式系统提供廉价、大容量的存储。

Opensource DDR3 Controller

A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs

🌊 一款 Material Design 风格的 Hexo 主题 / An elegant Material-Design theme for Hexo

A Wonderful Theme for Hexo.