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fix(aia): add the missing AIA-related permission checks #4166

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merged 4 commits into from
Jan 16, 2025
Merged

fix(aia): add the missing AIA-related permission checks #4166

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5fee746
fix(aia): add the missing AIA-related permission checks
NewPaulWalker Jan 13, 2025
f92761e
feat(difftest): sync hgeip by difftest
NewPaulWalker Jan 14, 2025
cde7408
submodule(difftest): bump difftest to support sync AIA
NewPaulWalker Jan 16, 2025
13166ca
submodule(ready-to-run): Bump nemu ref in ready-to-run
NewPaulWalker Jan 16, 2025
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2 changes: 1 addition & 1 deletion difftest
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Submodule difftest updated 7 files
+1 −1 README.md
+2 −1 src/main/scala/Bundles.scala
+2 −2 src/main/scala/Difftest.scala
+12 −11 src/test/csrc/difftest/difftest.cpp
+2 −2 src/test/csrc/difftest/difftest.h
+6 −5 src/test/csrc/difftest/refproxy.h
+1 −1 src/test/scala/DifftestTop.scala
2 changes: 1 addition & 1 deletion ready-to-run
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Submodule ready-to-run updated 4 files
+ − riscv64-nemu-interpreter-debug-so
+ − riscv64-nemu-interpreter-dual-debug-so
+ − riscv64-nemu-interpreter-dual-so
+ − riscv64-nemu-interpreter-so
2 changes: 1 addition & 1 deletion src/main/scala/xiangshan/backend/fu/NewCSR/CSRAIA.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -236,7 +236,7 @@ class CSRToAIABundle extends Bundle {
}

class AIAToCSRBundle extends Bundle {
private val NumVSIRFiles = 63
private val NumVSIRFiles = 5
val rdata = ValidIO(new Bundle {
val data = UInt(XLEN.W)
val illegal = Bool()
Expand Down
18 changes: 14 additions & 4 deletions src/main/scala/xiangshan/backend/fu/NewCSR/CSRPermitModule.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -65,15 +65,16 @@ class CSRPermitModule extends Module {
val pPermit_EX_II = privilegePermitMod.io.out.privilege_EX_II
val pPermit_EX_VI = privilegePermitMod.io.out.privilege_EX_VI

val vPermit_EX_II = virtualLevelPermitMod.io.out.virtualLevelPermit_EX_II
val vPermit_EX_VI = virtualLevelPermitMod.io.out.virtualLevelPermit_EX_VI

val indirectPermit_EX_II = indirectCSRPermitMod.io.out.indirectCSR_EX_II
val indirectPermit_EX_VI = indirectCSRPermitMod.io.out.indirectCSR_EX_VI

val directPermit_illegal = mPermit_EX_II || sPermit_EX_II || pPermit_EX_II || pPermit_EX_VI || vPermit_EX_VI
val directPermit_illegal = mPermit_EX_II || sPermit_EX_II || pPermit_EX_II || pPermit_EX_VI || vPermit_EX_II || vPermit_EX_VI

val csrAccess_EX_II = csrAccess && (
(mPermit_EX_II || sPermit_EX_II || pPermit_EX_II) ||
(mPermit_EX_II || sPermit_EX_II || pPermit_EX_II || vPermit_EX_II) ||
(!directPermit_illegal && indirectPermit_EX_II)
)
val csrAccess_EX_VI = csrAccess && (
Expand Down Expand Up @@ -380,6 +381,7 @@ class VirtualLevelPermitModule extends Module {
val aia = new aiaIO
})
val out = Output(new Bundle {
val virtualLevelPermit_EX_II = Bool()
val virtualLevelPermit_EX_VI = Bool()
})
})
Expand All @@ -390,7 +392,10 @@ class VirtualLevelPermitModule extends Module {
io.in.privState,
)

private val vtvm = io.in.status.vtvm
private val (vtvm, vgein) = (
io.in.status.vtvm,
io.in.status.vgein,
)

private val (hcounteren, scounteren) = (
io.in.xcounteren.hcounteren,
Expand All @@ -415,6 +420,9 @@ class VirtualLevelPermitModule extends Module {

private val rwSatp_EX_VI = privState.isModeVS && vtvm && (addr === CSRs.satp.U)

private val rwVStopei_EX_II = (privState.isModeM || privState.isModeHS) && (addr === CSRs.vstopei.U) && (vgein === 0.U || vgein > CSRConfig.GEILEN.U)
private val rwStopei_EX_VI = privState.isModeVS && (addr === CSRs.stopei.U) && (vgein === 0.U || vgein > CSRConfig.GEILEN.U)

private val rwSip_Sie_EX_VI = privState.isModeVS && hvictlVTI && (addr === CSRs.sip.U || addr === CSRs.sie.U)

private val rwStimecmp_EX_VI = privState.isModeVS && (addr === CSRs.stimecmp.U) &&
Expand Down Expand Up @@ -466,7 +474,8 @@ class VirtualLevelPermitModule extends Module {
private val xstateControlAccess_EX_VI = accessStateen0_EX_VI || accessEnvcfg_EX_VI || accessIND_EX_VI || accessAIA_EX_VI ||
accessTopie_EX_VI || accessContext_EX_VI || accessCustom_EX_VI

io.out.virtualLevelPermit_EX_VI := rwSatp_EX_VI || rwSip_Sie_EX_VI || rwStimecmp_EX_VI || accessHPM_EX_VI || xstateControlAccess_EX_VI
io.out.virtualLevelPermit_EX_II := rwVStopei_EX_II
io.out.virtualLevelPermit_EX_VI := rwSatp_EX_VI || rwStopei_EX_VI || rwSip_Sie_EX_VI || rwStimecmp_EX_VI || accessHPM_EX_VI || xstateControlAccess_EX_VI
}

class IndirectCSRPermitModule extends Module {
Expand Down Expand Up @@ -538,6 +547,7 @@ class statusIO extends Bundle {
val tvm = Bool()
// Virtual Trap Virtual Memory
val vtvm = Bool()
val vgein = UInt(6.W)
val mstatusFSOff = Bool()
val vsstatusFSOff = Bool()
val mstatusVSOff = Bool()
Expand Down
4 changes: 1 addition & 3 deletions src/main/scala/xiangshan/backend/fu/NewCSR/HypervisorLevel.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -219,9 +219,7 @@ class HstatusBundle extends CSRBundle {

}

object HstatusVgeinField extends CSREnum with WLRLApply {
override def isLegal(enumeration: CSREnumType): Bool = enumeration.asUInt <= GEILEN.U
}
object HstatusVgeinField extends CSREnum with WLRLApply

class HstatusModule(implicit p: Parameters) extends CSRModule("Hstatus", new HstatusBundle)
with SretEventSinkBundle
Expand Down
17 changes: 10 additions & 7 deletions src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -25,7 +25,7 @@ import xiangshan.backend.trace._
import scala.collection.immutable.SeqMap

object CSRConfig {
final val GEILEN = 63
final val GEILEN = 5 // m,s,5vs

final val ASIDLEN = 16 // the length of ASID of XS implementation

Expand Down Expand Up @@ -469,6 +469,8 @@ class NewCSR(implicit val p: Parameters) extends Module
permitMod.io.in.status.tvm := mstatus.regOut.TVM.asBool
permitMod.io.in.status.vtvm := hstatus.regOut.VTVM.asBool

permitMod.io.in.status.vgein := hstatus.regOut.VGEIN.asUInt

permitMod.io.in.xcounteren.mcounteren := mcounteren.rdata
permitMod.io.in.xcounteren.hcounteren := hcounteren.rdata
permitMod.io.in.xcounteren.scounteren := scounteren.rdata
Expand Down Expand Up @@ -1552,12 +1554,13 @@ class NewCSR(implicit val p: Parameters) extends Module
}).orR
diffMhpmeventOverflowEvent.mhpmeventOverflow := VecInit(mhpmevents.map(_.regOut.asInstanceOf[MhpmeventBundle].OF.asBool)).asUInt

val diffAIAXtopeiEvent = DifftestModule(new DiffAIAXtopeiEvent)
diffAIAXtopeiEvent.coreid := hartId
diffAIAXtopeiEvent.valid := fromAIA.rdata.valid
diffAIAXtopeiEvent.mtopei := mtopei.rdata
diffAIAXtopeiEvent.stopei := stopei.rdata
diffAIAXtopeiEvent.vstopei := vstopei.rdata
val diffSyncAIAEvent = DifftestModule(new DiffSyncAIAEvent)
diffSyncAIAEvent.coreid := hartId
diffSyncAIAEvent.valid := fromAIA.rdata.valid
diffSyncAIAEvent.mtopei := mtopei.rdata
diffSyncAIAEvent.stopei := stopei.rdata
diffSyncAIAEvent.vstopei := vstopei.rdata
diffSyncAIAEvent.hgeip := hgeip.rdata

val diffCustomMflushpwr = DifftestModule(new DiffSyncCustomMflushpwrEvent)
diffCustomMflushpwr.coreid := hartId
Expand Down
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