Park-Hyung-Joo
Follow
Stars
3
stars
written in Verilog
Clear filter
Standard Cell Library based Memory Compiler using FF/Latch cells
Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversi…
Fully-differential asynchronous non-binary 12-bit SAR-ADC