Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversi…

A python microframework for integer programming lagrangian relaxation

Implementation of Lagrangian Relaxation Method for approximating constrained optimization problems

A mutable, self-balancing interval tree. Queries may be by point, by range overlap, or by range containment.

theorydb's blog

Linear optimization software

This is my assignment on Andrew Ng's course “neural networks and deep learning”

The text for those who want to study reinforcement learning in Korean

Python script for generating lookup tables for the gm/ID design methodology and much more ...

Python module for creating GDSII stream files, usually CAD layouts.

A* (Astar / A Star) search algorithm. Easy to use

Scripts to download osic-tools docker image and run it directly in wsl (without docker)

Parser for LEF library files

Fully-differential asynchronous non-binary 12-bit SAR-ADC

Modular hardware build system

SKY130 ReRAM and examples (SkyWater Provided)

A RRAM addon for the NCSU FreePDK 45nm

python library to design chips (Photonics, Analog, Quantum, MEMs, ...), objects for 3D printing or PCBs.

This repo contains introduction of gm/id method and its application to some OTA design examples.

Ancillary Material for the book "Systematic Design of Analog CMOS Circuits"

Hardware Description Library

Hardware Design Tool - Mixed Signal Simulation with Verilog

Standard Cell Library based Memory Compiler using FF/Latch cells

LAYGO2 workspace for SKY130 open-source PDK. https://laygo2-sky130-docs.readthedocs.io/en/main

LAYout with Gridded Objects v2

Courseworks of CS6165 VLSI Physical Design Automation, NTHU.

⚡ Jekyll Theme Chripy 템플릿 포크해서 2020, 2021 바라미 전시회를 위한 바라미 블로그 개설 ⚡ 업로드하다 깃헙 잘 모르겠으면 질문은 신현(@kyaryunha) 에게 ㄱㄱ ⚡

A seamless python to Cadence Virtuoso Skill interface