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This patch adds support for the OT1200 series of devices. Following components are used in u-boot: + ethernet + i2c + emmc + gpio For more details see README. Changes v1 > v2 - make use of enable_cspi_clock(..) - fix usage of OUTPUT_40OHM define - added README Changes v2 > v3 - improve spelling in README - added own copy of mx6q_4x_mt41j128.cfg Signed-off-by: Christian Gmeiner <[email protected]>
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if TARGET_OT1200 | ||
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config SYS_CPU | ||
string | ||
default "armv7" | ||
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config SYS_BOARD | ||
string | ||
default "ot1200" | ||
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config SYS_VENDOR | ||
string | ||
default "bachmann" | ||
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config SYS_SOC | ||
string | ||
default "mx6" | ||
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config SYS_CONFIG_NAME | ||
string | ||
default "ot1200" | ||
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endif |
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BACHMANN ELECTRONIC OT1200 BOARD | ||
M: Christian Gmeiner <[email protected]> | ||
S: Maintained | ||
F: board/bachmann/ot1200 | ||
F: include/configs/ot1200.h | ||
F: configs/ot1200*_defconfig |
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# | ||
# Copyright (C) 2012-2013, Guennadi Liakhovetski <[email protected]> | ||
# (C) Copyright 2012-2013 Freescale Semiconductor, Inc. | ||
# Copyright (C) 2013, Boundary Devices <[email protected]> | ||
# | ||
# SPDX-License-Identifier: GPL-2.0+ | ||
# | ||
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obj-y := ot1200.o |
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U-Boot for the Bachmann electronic GmbH OT1200 devices | ||
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There are two different versions of the base board, which differ | ||
in the way ethernet is done. The variant detection is done during | ||
runtime based on the address of the found phy. | ||
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- "mr" variant | ||
FEC is connected directly to an ethernet switch (KSZ8895). The ethernet | ||
port is always up and auto-negotiation is not possible. | ||
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- normal variant | ||
FEC is connected to a normal phy and auto-negotiation is possible. | ||
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The variant name is part of the dtb file name loaded by u-boot. This | ||
make is possible to boot the linux kernel and make use variant specific | ||
devicetree (fixed-phy link). | ||
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In order to support different display resoltuions/sizes the OT1200 devices | ||
are making use of EDID data stored in an i2c EEPROM. |
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/* | ||
* Copyright (C) 2011 Freescale Semiconductor, Inc. | ||
* Jason Liu <[email protected]> | ||
* | ||
* SPDX-License-Identifier: GPL-2.0+ | ||
* | ||
* Refer doc/README.imximage for more details about how-to configure | ||
* and create imximage boot image | ||
* | ||
* The syntax is taken as close as possible with the kwbimage | ||
*/ | ||
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/* image version */ | ||
IMAGE_VERSION 2 | ||
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/* | ||
* Boot Device : one of | ||
* spi, sd (the board has no nand neither onenand) | ||
*/ | ||
BOOT_FROM sd | ||
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/* | ||
* Device Configuration Data (DCD) | ||
* | ||
* Each entry must have the format: | ||
* Addr-type Address Value | ||
* | ||
* where: | ||
* Addr-type register length (1,2 or 4 bytes) | ||
* Address absolute address of the register | ||
* value value to be stored in the register | ||
*/ | ||
DATA 4 0x020e05a8 0x00000030 | ||
DATA 4 0x020e05b0 0x00000030 | ||
DATA 4 0x020e0524 0x00000030 | ||
DATA 4 0x020e051c 0x00000030 | ||
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DATA 4 0x020e0518 0x00000030 | ||
DATA 4 0x020e050c 0x00000030 | ||
DATA 4 0x020e05b8 0x00000030 | ||
DATA 4 0x020e05c0 0x00000030 | ||
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DATA 4 0x020e05ac 0x00020030 | ||
DATA 4 0x020e05b4 0x00020030 | ||
DATA 4 0x020e0528 0x00020030 | ||
DATA 4 0x020e0520 0x00020030 | ||
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DATA 4 0x020e0514 0x00020030 | ||
DATA 4 0x020e0510 0x00020030 | ||
DATA 4 0x020e05bc 0x00020030 | ||
DATA 4 0x020e05c4 0x00020030 | ||
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DATA 4 0x020e056c 0x00020030 | ||
DATA 4 0x020e0578 0x00020030 | ||
DATA 4 0x020e0588 0x00020030 | ||
DATA 4 0x020e0594 0x00020030 | ||
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DATA 4 0x020e057c 0x00020030 | ||
DATA 4 0x020e0590 0x00003000 | ||
DATA 4 0x020e0598 0x00003000 | ||
DATA 4 0x020e058c 0x00000000 | ||
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DATA 4 0x020e059c 0x00003030 | ||
DATA 4 0x020e05a0 0x00003030 | ||
DATA 4 0x020e0784 0x00000030 | ||
DATA 4 0x020e0788 0x00000030 | ||
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DATA 4 0x020e0794 0x00000030 | ||
DATA 4 0x020e079c 0x00000030 | ||
DATA 4 0x020e07a0 0x00000030 | ||
DATA 4 0x020e07a4 0x00000030 | ||
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DATA 4 0x020e07a8 0x00000030 | ||
DATA 4 0x020e0748 0x00000030 | ||
DATA 4 0x020e074c 0x00000030 | ||
DATA 4 0x020e0750 0x00020000 | ||
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DATA 4 0x020e0758 0x00000000 | ||
DATA 4 0x020e0774 0x00020000 | ||
DATA 4 0x020e078c 0x00000030 | ||
DATA 4 0x020e0798 0x000C0000 | ||
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DATA 4 0x021b081c 0x33333333 | ||
DATA 4 0x021b0820 0x33333333 | ||
DATA 4 0x021b0824 0x33333333 | ||
DATA 4 0x021b0828 0x33333333 | ||
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DATA 4 0x021b481c 0x33333333 | ||
DATA 4 0x021b4820 0x33333333 | ||
DATA 4 0x021b4824 0x33333333 | ||
DATA 4 0x021b4828 0x33333333 | ||
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DATA 4 0x021b0018 0x00081740 | ||
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DATA 4 0x021b001c 0x00008000 | ||
DATA 4 0x021b000c 0x555A7974 | ||
DATA 4 0x021b0010 0xDB538F64 | ||
DATA 4 0x021b0014 0x01FF00DB | ||
DATA 4 0x021b002c 0x000026D2 | ||
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DATA 4 0x021b0030 0x005A1023 | ||
DATA 4 0x021b0008 0x09444040 | ||
DATA 4 0x021b0004 0x00025576 | ||
DATA 4 0x021b0040 0x00000027 | ||
DATA 4 0x021b0000 0x831A0000 | ||
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DATA 4 0x021b001c 0x04088032 | ||
DATA 4 0x021b001c 0x0408803A | ||
DATA 4 0x021b001c 0x00008033 | ||
DATA 4 0x021b001c 0x0000803B | ||
DATA 4 0x021b001c 0x00428031 | ||
DATA 4 0x021b001c 0x00428039 | ||
DATA 4 0x021b001c 0x19308030 | ||
DATA 4 0x021b001c 0x19308038 | ||
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DATA 4 0x021b001c 0x04008040 | ||
DATA 4 0x021b001c 0x04008048 | ||
DATA 4 0x021b0800 0xA1380003 | ||
DATA 4 0x021b4800 0xA1380003 | ||
DATA 4 0x021b0020 0x00005800 | ||
DATA 4 0x021b0818 0x00022227 | ||
DATA 4 0x021b4818 0x00022227 | ||
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DATA 4 0x021b083c 0x434B0350 | ||
DATA 4 0x021b0840 0x034C0359 | ||
DATA 4 0x021b483c 0x434B0350 | ||
DATA 4 0x021b4840 0x03650348 | ||
DATA 4 0x021b0848 0x4436383B | ||
DATA 4 0x021b4848 0x39393341 | ||
DATA 4 0x021b0850 0x35373933 | ||
DATA 4 0x021b4850 0x48254A36 | ||
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DATA 4 0x021b080c 0x001F001F | ||
DATA 4 0x021b0810 0x001F001F | ||
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DATA 4 0x021b480c 0x00440044 | ||
DATA 4 0x021b4810 0x00440044 | ||
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DATA 4 0x021b08b8 0x00000800 | ||
DATA 4 0x021b48b8 0x00000800 | ||
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DATA 4 0x021b001c 0x00000000 | ||
DATA 4 0x021b0404 0x00011006 | ||
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/* set the default clock gate to save power */ | ||
DATA 4 0x020c4068 0x00C03F3F | ||
DATA 4 0x020c406c 0x0030FC03 | ||
DATA 4 0x020c4070 0x0FFFC000 | ||
DATA 4 0x020c4074 0x3FF00000 | ||
DATA 4 0x020c4078 0x00FFF300 | ||
DATA 4 0x020c407c 0x0F0000C3 | ||
DATA 4 0x020c4080 0x000003FF | ||
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/* enable AXI cache for VDOA/VPU/IPU */ | ||
DATA 4 0x020e0010 0xF00000CF | ||
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ | ||
DATA 4 0x020e0018 0x007F007F | ||
DATA 4 0x020e001c 0x007F007F | ||
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/* | ||
* Setup CCM_CCOSR register as follows: | ||
* | ||
* cko1_en = 1 --> CKO1 enabled | ||
* cko1_div = 111 --> divide by 8 | ||
* cko1_sel = 1011 --> ahb_clk_root | ||
* | ||
* This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz | ||
*/ | ||
DATA 4 0x020c4060 0x000000fb |
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