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Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boo…
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…t-spi into next

- Cypress s25hl-t/s25hs-t support (Takahiro Kuwano)
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@trini
trini committed Jun 30, 2021
2 parents 8fba49b + 5b8ec59 commit 90c2fd2
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Showing 4 changed files with 297 additions and 2 deletions.
266 changes: 264 additions & 2 deletions drivers/mtd/spi/spi-nor-core.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -315,6 +315,31 @@ static int spi_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
return spi_nor_read_write_reg(nor, &op, buf);
}

#ifdef CONFIG_SPI_FLASH_SPANSION
static int spansion_read_any_reg(struct spi_nor *nor, u32 addr, u8 dummy,
u8 *val)
{
struct spi_mem_op op =
SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDAR, 1),
SPI_MEM_OP_ADDR(nor->addr_width, addr, 1),
SPI_MEM_OP_DUMMY(dummy / 8, 1),
SPI_MEM_OP_DATA_IN(1, NULL, 1));

return spi_nor_read_write_reg(nor, &op, val);
}

static int spansion_write_any_reg(struct spi_nor *nor, u32 addr, u8 val)
{
struct spi_mem_op op =
SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRAR, 1),
SPI_MEM_OP_ADDR(nor->addr_width, addr, 1),
SPI_MEM_OP_NO_DUMMY,
SPI_MEM_OP_DATA_OUT(1, NULL, 1));

return spi_nor_read_write_reg(nor, &op, &val);
}
#endif

static ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len,
u_char *buf)
{
Expand Down Expand Up @@ -637,13 +662,45 @@ static int set_4byte(struct spi_nor *nor, const struct flash_info *info,
}

return status;
case SNOR_MFR_CYPRESS:
cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B_CYPRESS;
return nor->write_reg(nor, cmd, NULL, 0);
default:
/* Spansion style */
nor->cmd_buf[0] = enable << 7;
return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1);
}
}

#ifdef CONFIG_SPI_FLASH_SPANSION
/*
* Read status register 1 by using Read Any Register command to support multi
* die package parts.
*/
static int spansion_sr_ready(struct spi_nor *nor, u32 addr_base, u8 dummy)
{
u32 reg_addr = addr_base + SPINOR_REG_ADDR_STR1V;
u8 sr;
int ret;

ret = spansion_read_any_reg(nor, reg_addr, dummy, &sr);
if (ret < 0)
return ret;

if (sr & (SR_E_ERR | SR_P_ERR)) {
if (sr & SR_E_ERR)
dev_dbg(nor->dev, "Erase Error occurred\n");
else
dev_dbg(nor->dev, "Programming Error occurred\n");

nor->write_reg(nor, SPINOR_OP_CLSR, NULL, 0);
return -EIO;
}

return !(sr & SR_WIP);
}
#endif

static int spi_nor_sr_ready(struct spi_nor *nor)
{
int sr = read_sr(nor);
Expand Down Expand Up @@ -688,7 +745,7 @@ static int spi_nor_fsr_ready(struct spi_nor *nor)
return fsr & FSR_READY;
}

static int spi_nor_ready(struct spi_nor *nor)
static int spi_nor_default_ready(struct spi_nor *nor)
{
int sr, fsr;

Expand All @@ -701,6 +758,14 @@ static int spi_nor_ready(struct spi_nor *nor)
return sr && fsr;
}

static int spi_nor_ready(struct spi_nor *nor)
{
if (nor->ready)
return nor->ready(nor);

return spi_nor_default_ready(nor);
}

/*
* Service routine to read status register until ready, or timeout occurs.
* Returns non-zero if error.
Expand Down Expand Up @@ -887,7 +952,7 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
return ret;
}

#ifdef CONFIG_SPI_FLASH_S28HS512T
#ifdef CONFIG_SPI_FLASH_SPANSION
/**
* spansion_erase_non_uniform() - erase non-uniform sectors for Spansion/Cypress
* chips
Expand Down Expand Up @@ -1686,6 +1751,61 @@ static int macronix_quad_enable(struct spi_nor *nor)
}
#endif

#ifdef CONFIG_SPI_FLASH_SPANSION
/**
* spansion_quad_enable_volatile() - enable Quad I/O mode in volatile register.
* @nor: pointer to a 'struct spi_nor'
* @addr_base: base address of register (can be >0 in multi-die parts)
* @dummy: number of dummy cycles for register read
*
* It is recommended to update volatile registers in the field application due
* to a risk of the non-volatile registers corruption by power interrupt. This
* function sets Quad Enable bit in CFR1 volatile.
*
* Return: 0 on success, -errno otherwise.
*/
static int spansion_quad_enable_volatile(struct spi_nor *nor, u32 addr_base,
u8 dummy)
{
u32 addr = addr_base + SPINOR_REG_ADDR_CFR1V;

u8 cr;
int ret;

/* Check current Quad Enable bit value. */
ret = spansion_read_any_reg(nor, addr, dummy, &cr);
if (ret < 0) {
dev_dbg(nor->dev,
"error while reading configuration register\n");
return -EINVAL;
}

if (cr & CR_QUAD_EN_SPAN)
return 0;

cr |= CR_QUAD_EN_SPAN;

write_enable(nor);

ret = spansion_write_any_reg(nor, addr, cr);

if (ret < 0) {
dev_dbg(nor->dev,
"error while writing configuration register\n");
return -EINVAL;
}

/* Read back and check it. */
ret = spansion_read_any_reg(nor, addr, dummy, &cr);
if (ret || !(cr & CR_QUAD_EN_SPAN)) {
dev_dbg(nor->dev, "Spansion Quad bit not set\n");
return -EINVAL;
}

return 0;
}
#endif

#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
/*
* Write status Register and configuration register with 2 bytes
Expand Down Expand Up @@ -2965,6 +3085,134 @@ static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info,
return nor->setup(nor, info, params);
}

#ifdef CONFIG_SPI_FLASH_SPANSION
static int s25hx_t_mdp_ready(struct spi_nor *nor)
{
u32 addr;
int ret;

for (addr = 0; addr < nor->mtd.size; addr += SZ_128M) {
ret = spansion_sr_ready(nor, addr, 0);
if (!ret)
return ret;
}

return 1;
}

static int s25hx_t_quad_enable(struct spi_nor *nor)
{
u32 addr;
int ret;

for (addr = 0; addr < nor->mtd.size; addr += SZ_128M) {
ret = spansion_quad_enable_volatile(nor, addr, 0);
if (ret)
return ret;
}

return 0;
}

static int s25hx_t_erase_non_uniform(struct spi_nor *nor, loff_t addr)
{
/* Support 32 x 4KB sectors at bottom */
return spansion_erase_non_uniform(nor, addr, SPINOR_OP_BE_4K_4B, 0,
SZ_128K);
}

static int s25hx_t_setup(struct spi_nor *nor, const struct flash_info *info,
const struct spi_nor_flash_parameter *params)
{
int ret;
u8 cfr3v;

#ifdef CONFIG_SPI_FLASH_BAR
return -ENOTSUPP; /* Bank Address Register is not supported */
#endif
/*
* Read CFR3V to check if uniform sector is selected. If not, assign an
* erase hook that supports non-uniform erase.
*/
ret = spansion_read_any_reg(nor, SPINOR_REG_ADDR_CFR3V, 0, &cfr3v);
if (ret)
return ret;
if (!(cfr3v & CFR3V_UNHYSA))
nor->erase = s25hx_t_erase_non_uniform;

/*
* For the multi-die package parts, the ready() hook is needed to check
* all dies' status via read any register.
*/
if (nor->mtd.size > SZ_128M)
nor->ready = s25hx_t_mdp_ready;

return spi_nor_default_setup(nor, info, params);
}

static void s25hx_t_default_init(struct spi_nor *nor)
{
nor->setup = s25hx_t_setup;
}

static int s25hx_t_post_bfpt_fixup(struct spi_nor *nor,
const struct sfdp_parameter_header *header,
const struct sfdp_bfpt *bfpt,
struct spi_nor_flash_parameter *params)
{
int ret;
u32 addr;
u8 cfr3v;

/* erase size in case it is set to 4K from BFPT */
nor->erase_opcode = SPINOR_OP_SE_4B;
nor->mtd.erasesize = nor->info->sector_size;

ret = set_4byte(nor, nor->info, 1);
if (ret)
return ret;
nor->addr_width = 4;

/*
* The page_size is set to 512B from BFPT, but it actually depends on
* the configuration register. Look up the CFR3V and determine the
* page_size. For multi-die package parts, use 512B only when the all
* dies are configured to 512B buffer.
*/
for (addr = 0; addr < params->size; addr += SZ_128M) {
ret = spansion_read_any_reg(nor, addr + SPINOR_REG_ADDR_CFR3V,
0, &cfr3v);
if (ret)
return ret;

if (!(cfr3v & CFR3V_PGMBUF)) {
params->page_size = 256;
return 0;
}
}
params->page_size = 512;

return 0;
}

static void s25hx_t_post_sfdp_fixup(struct spi_nor *nor,
struct spi_nor_flash_parameter *params)
{
/* READ_FAST_4B (0Ch) requires mode cycles*/
params->reads[SNOR_CMD_READ_FAST].num_mode_clocks = 8;
/* PP_1_1_4 is not supported */
params->hwcaps.mask &= ~SNOR_HWCAPS_PP_1_1_4;
/* Use volatile register to enable quad */
params->quad_enable = s25hx_t_quad_enable;
}

static struct spi_nor_fixups s25hx_t_fixups = {
.default_init = s25hx_t_default_init,
.post_bfpt = s25hx_t_post_bfpt_fixup,
.post_sfdp = s25hx_t_post_sfdp_fixup,
};
#endif

#ifdef CONFIG_SPI_FLASH_S28HS512T
/**
* spi_nor_cypress_octal_dtr_enable() - Enable octal DTR on Cypress flashes.
Expand Down Expand Up @@ -3373,6 +3621,20 @@ int spi_nor_remove(struct spi_nor *nor)

void spi_nor_set_fixups(struct spi_nor *nor)
{
#ifdef CONFIG_SPI_FLASH_SPANSION
if (JEDEC_MFR(nor->info) == SNOR_MFR_CYPRESS) {
switch (nor->info->id[1]) {
case 0x2a: /* S25HL (QSPI, 3.3V) */
case 0x2b: /* S25HS (QSPI, 1.8V) */
nor->fixups = &s25hx_t_fixups;
break;

default:
break;
}
}
#endif

#ifdef CONFIG_SPI_FLASH_S28HS512T
if (!strcmp(nor->info->name, "s28hs512t"))
nor->fixups = &s28hs512t_fixups;
Expand Down
16 changes: 16 additions & 0 deletions drivers/mtd/spi/spi-nor-ids.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -225,6 +225,22 @@ const struct flash_info spi_nor_ids[] = {
{ INFO("s25fl208k", 0x014014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ) },
{ INFO("s25fl064l", 0x016017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
{ INFO("s25fl128l", 0x016018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
{ INFO6("s25hl512t", 0x342a1a, 0x0f0390, 256 * 1024, 256,
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES |
USE_CLSR) },
{ INFO6("s25hl01gt", 0x342a1b, 0x0f0390, 256 * 1024, 512,
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES |
USE_CLSR) },
{ INFO6("s25hl02gt", 0x342a1c, 0x0f0090, 256 * 1024, 1024,
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
{ INFO6("s25hs512t", 0x342b1a, 0x0f0390, 256 * 1024, 256,
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES |
USE_CLSR) },
{ INFO6("s25hs01gt", 0x342b1b, 0x0f0390, 256 * 1024, 512,
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES |
USE_CLSR) },
{ INFO6("s25hs02gt", 0x342b1c, 0x0f0090, 256 * 1024, 1024,
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
#ifdef CONFIG_SPI_FLASH_S28HS512T
{ INFO("s28hs512t", 0x345b1a, 0, 256 * 1024, 256, SPI_NOR_OCTAL_DTR_READ) },
#endif
Expand Down
6 changes: 6 additions & 0 deletions drivers/mtd/spi/spi-nor-tiny.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -583,6 +583,12 @@ static int spi_nor_init_params(struct spi_nor *nor,
spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_FAST],
0, 8, SPINOR_OP_READ_FAST,
SNOR_PROTO_1_1_1);
#ifdef CONFIG_SPI_FLASH_SPANSION
if (JEDEC_MFR(info) == SNOR_MFR_CYPRESS &&
(info->id[1] == 0x2a || info->id[1] == 0x2b))
/* 0x2a: S25HL (QSPI, 3.3V), 0x2b: S25HS (QSPI, 1.8V) */
params->reads[SNOR_CMD_READ_FAST].num_mode_clocks = 8;
#endif
}

if (info->flags & SPI_NOR_QUAD_READ) {
Expand Down
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