(All projects were done in Xilinx Vivado 2018 ) (If there were demonstrations, then they were done on Artix 7 100T FPGA board)
The objective of this lab was to verify the functionality of the VHDL design from Lab A onto the Xilinx FPGA board by generating a bitstream of the design through synthesis and implementation.
The objective of this lab was to practice generating timing simulations on Xilinx Vivado and demonstrating various designs, such as the majority circuit and full adder, on the Nexys FPGA through synthesis and implementation of that gate-version design.
The objective of this lab was to design, simulate, and implement a 4-bit comparator in Verilog through instantiation of 2-bit comparator. This design will be synthesized, implemented, and the bitstream will be downloaded onto the Nexys A7 FPGA board. In addition, a 7-segment decoder was also designed, synthesized, and implemented onto the FPGA board to display the HEX LEDs.
The objective of this lab is to design and simulate an Arithmetic Logic Unit (ALU) in Verilog using the Xilinx Vivado 2018 IDE. The design will also be performed on the Nexys A7 FPGA board through the generation of the bitstream from the synthesis and implementation process.
The objective of this lab was to model and simulate a 4x4 array multiplier using Vivado. The array multiplier will also be implemented onto the NEXYS A7 FPGA board through the download of the synthesized multiplier design onto the board.
The objective of this lab was to understand the behavior of latches and flip flops by creating logical models in Verilog and simulating them on Xilinx Vivado 2018. Some of the models were further demonstrated on the Nexys A7 100T FPGA board.
The objective of this lab was to run a 4-bit HEX counter design in Verilog on the Nexys A7 100T FPGA board using Xilinx Vivado.
The objective of this lab is to use multiple 7-segment displays through the process of aggregation, which will involve the use of two 7 segment displays.