Vlv2TbltDevicePkg: Sync the branch changes to trunk.

Support compatible board, and fixed some bugs. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Tim He <[email protected]> Reviewed-by: David Wei <[email protected]> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18149 6f19259b-4bc3-4df7-8a09-765794883524
QUSIR · Aug 4, 2015 · 6f2ef18 · 6f2ef18
1 parent c5d5379
commit 6f2ef18
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Showing 23 changed files with 215 additions and 56 deletions.
diff --git a/Vlv2TbltDevicePkg/BiosIdD.env b/Vlv2TbltDevicePkg/BiosIdD.env
@@ -26,5 +26,5 @@ OEM_ID        = I32
 BUILD_TYPE    = D
 
 BOARD_ID = BLAKCRB
-VERSION_MAJOR = 0080
+VERSION_MAJOR = 0083
 VERSION_MINOR = 01

diff --git a/Vlv2TbltDevicePkg/BiosIdR.env b/Vlv2TbltDevicePkg/BiosIdR.env
@@ -26,5 +26,5 @@ OEM_ID        = I32
 BUILD_TYPE    = R
 
 BOARD_ID = BLAKCRB
-VERSION_MAJOR = 0080
+VERSION_MAJOR = 0083
 VERSION_MINOR = 01

diff --git a/Vlv2TbltDevicePkg/BiosIdx64D.env b/Vlv2TbltDevicePkg/BiosIdx64D.env
@@ -25,6 +25,6 @@ BOARD_REV     = 1
 OEM_ID        = X64
 BUILD_TYPE    = D
 
-VERSION_MAJOR = 0080
+VERSION_MAJOR = 0083
 VERSION_MINOR = 01
 BOARD_ID = BBAYCRB 

diff --git a/Vlv2TbltDevicePkg/BiosIdx64R.env b/Vlv2TbltDevicePkg/BiosIdx64R.env
@@ -25,6 +25,6 @@ BOARD_REV     = 1
 OEM_ID        = X64
 BUILD_TYPE    = R
 
-VERSION_MAJOR = 0080
+VERSION_MAJOR = 0083
 VERSION_MINOR = 01
 BOARD_ID = BBAYCRB 

diff --git a/Vlv2TbltDevicePkg/Include/Guid/PlatformInfo.h b/Vlv2TbltDevicePkg/Include/Guid/PlatformInfo.h
@@ -176,7 +176,8 @@ typedef enum {
   BOARD_ID_BB_RVP   = 0x20,   // Bayley Bay Board
   BOARD_ID_BS_RVP   = 0x30,   // Bakersport Board
   BOARD_ID_CVH      = 0x90,   // Crestview Hills
-  BOARD_ID_MINNOW2  = 0xA0    // Minnow2
+  BOARD_ID_MINNOW2  = 0xA0,    // Minnow2
+  BOARD_ID_MINNOW2_COMPATIBLE  = 0xB0    // Minnow2
 
 } BOARD_ID_LIST;
 

diff --git a/Vlv2TbltDevicePkg/Include/Library/SpiFlash.H b/Vlv2TbltDevicePkg/Include/Library/SpiFlash.H
@@ -66,7 +66,7 @@ typedef enum {
 #define SF_DEVICE_ID0_W25XXX        0x30
 #define SF_DEVICE_ID1_W25X32        0x16
 #define SF_DEVICE_ID1_W25X64        0x17
-#define SF_DEVICE_ID0_W25QXX        0x60
+#define SF_DEVICE_ID0_W25QXX        0x40
 #define SF_DEVICE_ID1_W25Q16        0x15
 #define SF_DEVICE_ID1_W25Q32        0x16
 #define SF_DEVICE_ID1_W25Q64        0x17
@@ -152,7 +152,7 @@ typedef enum {
 
 #define SF_VENDOR_ID_WINBOND       0xEF
 #define SF_DEVICE_ID0_W25XXX       0x30
-#define SF_DEVICE_ID0_W25QXX       0x60
+
 #define SF_DEVICE_ID1_W25X80       0x14
 #define SF_DEVICE_ID1_W25X16       0x15
 #define SF_DEVICE_ID1_W25X32       0x16

diff --git a/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardClkGens/BoardClkGens.c b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardClkGens/BoardClkGens.c
@@ -370,6 +370,7 @@ ConfigurePlatformClocks (
 
   switch (PlatformInfoHob->BoardId) {
     case BOARD_ID_MINNOW2:
+    case BOARD_ID_MINNOW2_COMPATIBLE:
     default:
       switch(PlatformInfoHob->PlatformFlavor) {
       case FlavorTablet:

diff --git a/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardGpios/BoardGpios.c b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardGpios/BoardGpios.c
@@ -150,7 +150,7 @@ MultiPlatformGpioTableInit (
   switch (PlatformInfoHob->BoardId) {
 
   case BOARD_ID_MINNOW2: // Minnow2
-
+  case BOARD_ID_MINNOW2_COMPATIBLE: 
    Status = (**PeiServices).LocatePpi (
                              PeiServices,
                              &gEfiPeiReadOnlyVariable2PpiGuid,
@@ -509,6 +509,7 @@ MultiPlatformGpioProgram (
   //
   switch (PlatformInfoHob->BoardId) {
     case BOARD_ID_MINNOW2:
+    case BOARD_ID_MINNOW2_COMPATIBLE:
       DEBUG ((EFI_D_INFO, "Start to config Minnow2 GPIO pins\n"));
       InternalGpioConfig(GPIO_SCORE_OFFSET, sizeof(mMinnow2_GpioInitData_SC)/sizeof(mMinnow2_GpioInitData_SC[0]),   (GPIO_CONF_PAD_INIT *) (UINTN) PlatformInfoHob->PlatformGpioData_SC);
       InternalGpioConfig(GPIO_NCORE_OFFSET, sizeof(mMinnow2_GpioInitData_NC)/sizeof(mMinnow2_GpioInitData_NC[0]),   (GPIO_CONF_PAD_INIT *) (UINTN) PlatformInfoHob->PlatformGpioData_NC);
@@ -523,7 +524,7 @@ MultiPlatformGpioProgram (
    // configure the CFIO Pnp settings
    //
    if (PlatformInfoHob->CfioEnabled) {
-     if (PlatformInfoHob->BoardId == BOARD_ID_MINNOW2){
+     if (PlatformInfoHob->BoardId == BOARD_ID_MINNOW2 || PlatformInfoHob->BoardId == BOARD_ID_MINNOW2_COMPATIBLE){
        InternalGpioConfig(GPIO_SCORE_OFFSET, sizeof(mNB_BB_FAB3_GpioInitData_SC_TRI)/sizeof(mNB_BB_FAB3_GpioInitData_SC_TRI[0]), (GPIO_CONF_PAD_INIT *) (UINTN)PlatformInfoHob->PlatformGpioData_SC_TRI);
      }
    }

diff --git a/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardGpios/BoardGpios.h b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardGpios/BoardGpios.h
@@ -46,33 +46,33 @@ GPIO_INIT_ITEM("PLT_CLK3          GPIOC_99 "     ,TRISTS   ,NA           ,F0
 #define MINNOW2_GPIO_USE_SEL_VAL_64_70       0x00000000
 #define MINNOW2_GPIO_USE_SEL_VAL_64_70       0x00000000
 #define MINNOW2_GPIO_USE_SEL_VAL_SUS         0x00000000
-#define MINNOW2_GPIO_USE_SEL_VAL_SUS2        0x00000007
+#define MINNOW2_GPIO_USE_SEL_VAL_SUS2        0x00000001
 
 
 #define MINNOW2_GPIO_IO_SEL_VAL_0_31         0x00000000
 #define MINNOW2_GPIO_IO_SEL_VAL_32_63        0x00000000
 #define MINNOW2_GPIO_IO_SEL_VAL_64_70        0x00000000
 #define MINNOW2_GPIO_IO_SEL_VAL_SUS          0x00000000
-#define MINNOW2_GPIO_IO_SEL_VAL_SUS2         0x00000007   
+#define MINNOW2_GPIO_IO_SEL_VAL_SUS2         0x00000001   
 
 
 #define MINNOW2_GPIO_LVL_VAL_0_31            0x00000000
 #define MINNOW2_GPIO_LVL_VAL_32_63           0x00000000
 #define MINNOW2_GPIO_LVL_VAL_64_70           0x00000000
 #define MINNOW2_GPIO_LVL_VAL_SUS             0x00000000
-#define MINNOW2_GPIO_LVL_VAL_SUS2            0x00000007   
+#define MINNOW2_GPIO_LVL_VAL_SUS2            0x00000001   
 
 #define MINNOW2_GPIO_TPE_VAL_0_31            0x00000000
 #define MINNOW2_GPIO_TPE_VAL_SUS             0x00000000
-#define MINNOW2_GPIO_TPE_VAL_SUS2            0x00000007   
+#define MINNOW2_GPIO_TPE_VAL_SUS2            0x00000001   
 
 #define MINNOW2_GPIO_TNE_VAL_0_31            0x00000000
 #define MINNOW2_GPIO_TNE_VAL_SUS             0x00000000
-#define MINNOW2_GPIO_TNE_VAL_SUS2            0x00000007   
+#define MINNOW2_GPIO_TNE_VAL_SUS2            0x00000001  
 
 #define MINNOW2_GPIO_TS_VAL_0_31             0x00000000
 #define MINNOW2_GPIO_TS_VAL_SUS              0x00000000
-#define MINNOW2_GPIO_TS_VAL_SUS2             0x00000007   
+#define MINNOW2_GPIO_TS_VAL_SUS2             0x00000001   
 
 static CFIO_INIT_STRUCT mMinnow2CfioInitData =
 {

diff --git a/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardOemIds/BoardOemIds.c b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardOemIds/BoardOemIds.c
@@ -34,6 +34,7 @@ InitializeBoardOemId (
     switch (PlatformInfoHob->BoardId) {
 
       case BOARD_ID_MINNOW2:
+      case BOARD_ID_MINNOW2_COMPATIBLE:
       default:
         OemId = EFI_ACPI_OEM_ID_DEFAULT;
         OemTableId = EFI_ACPI_OEM_TABLE_ID_DEFAULT;

diff --git a/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardSsidSvid/BoardSsidSvid.c b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardSsidSvid/BoardSsidSvid.c
@@ -32,9 +32,10 @@ InitializeBoardSsidSvid (
     //
     switch (PlatformInfoHob->BoardId) {
       case BOARD_ID_MINNOW2:
-             default:
-                  SsidSvidValue = SUBSYSTEM_SVID_SSID;//SUBSYSTEM_SVID_SSID_DEFAULT;
-                  break;
+      case BOARD_ID_MINNOW2_COMPATIBLE:
+      default:
+        SsidSvidValue = SUBSYSTEM_SVID_SSID;//SUBSYSTEM_SVID_SSID_DEFAULT;
+        break;
       }
     PlatformInfoHob->SsidSvid = SsidSvidValue;
     return  EFI_SUCCESS;

diff --git a/Vlv2TbltDevicePkg/PlatformDxe/Platform.c b/Vlv2TbltDevicePkg/PlatformDxe/Platform.c
@@ -482,18 +482,6 @@ SpiBiosProtectionFunction(
     B_PCH_SPI_PR0_RPE|B_PCH_SPI_PR0_WPE|\
     (B_PCH_SPI_PR0_PRB_MASK&(BiosFlaLower0>>12))|(B_PCH_SPI_PR0_PRL_MASK&(BiosFlaLimit0>>12)<<16));
 
-  //
-  //Lock down PR0
-  //
-  MmioOr16 ((UINTN) (SpiBase + R_PCH_SPI_HSFS), (UINT16) (B_PCH_SPI_HSFS_FLOCKDN));
-
-  //
-  // Verify if it's really locked.
-  //
-  if ((MmioRead16 (SpiBase + R_PCH_SPI_HSFS) & B_PCH_SPI_HSFS_FLOCKDN) == 0) {
-    DEBUG((EFI_D_ERROR, "Failed to lock down PR0.\n"));
-  }
-
   //
   //Set PR1
   //
@@ -503,15 +491,15 @@ SpiBiosProtectionFunction(
     (B_PCH_SPI_PR1_PRB_MASK&(BiosFlaLower1>>12))|(B_PCH_SPI_PR1_PRL_MASK&(BiosFlaLimit1>>12)<<16));
 
   //
-  //Lock down PR1
+  //Lock down PRx
   //
   MmioOr16 ((UINTN) (SpiBase + R_PCH_SPI_HSFS), (UINT16) (B_PCH_SPI_HSFS_FLOCKDN));
 
   //
   // Verify if it's really locked.
   //
   if ((MmioRead16 (SpiBase + R_PCH_SPI_HSFS) & B_PCH_SPI_HSFS_FLOCKDN) == 0) {
-    DEBUG((EFI_D_ERROR, "Failed to lock down PR1.\n"));
+    DEBUG((EFI_D_ERROR, "Failed to lock down PRx.\n"));
   }
   return;
 
@@ -576,6 +564,32 @@ InitPciDevPME (
   }
 }
 
+VOID
+EFIAPI
+InitThermalZone (
+  EFI_EVENT  Event,
+  VOID       *Context
+  )
+{
+  UINTN                  VarSize;
+  EFI_STATUS             Status;
+  EFI_GLOBAL_NVS_AREA_PROTOCOL       *GlobalNvsArea;
+  VarSize = sizeof(SYSTEM_CONFIGURATION);
+  Status = gRT->GetVariable(
+                  NORMAL_SETUP_NAME,
+                  &gEfiNormalSetupGuid,
+                  NULL,
+                  &VarSize,
+                  &mSystemConfiguration
+                  );
+  Status = gBS->LocateProtocol (
+                  &gEfiGlobalNvsAreaProtocolGuid,
+                  NULL,
+                  (void **)&GlobalNvsArea
+                  );
+  GlobalNvsArea->Area->CriticalThermalTripPoint = mSystemConfiguration.CriticalThermalTripPoint;
+  GlobalNvsArea->Area->PassiveThermalTripPoint = mSystemConfiguration.PassiveThermalTripPoint;
+}
 #if defined SUPPORT_LVDS_DISPLAY && SUPPORT_LVDS_DISPLAY
 
 #endif
@@ -830,7 +844,16 @@ InitializePlatform (
                &mReadyToBootEvent
                );
   }
-
+  //
+  // Create a ReadyToBoot Event to run the thermalzone init process
+  //
+  Status = EfiCreateEventReadyToBootEx (
+             TPL_CALLBACK,
+             InitThermalZone,
+             NULL,
+             &mReadyToBootEvent
+             );  
+
   ReportStatusCodeEx (
     EFI_PROGRESS_CODE,
     EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_DXE_STEP1,

diff --git a/Vlv2TbltDevicePkg/PlatformInitPei/PlatformEarlyInit.c b/Vlv2TbltDevicePkg/PlatformInitPei/PlatformEarlyInit.c
@@ -905,6 +905,7 @@ PlatformEarlyInitEntry (
       PlatformInfo->BoardId == BOARD_ID_BB_RVP ||
       PlatformInfo->BoardId == BOARD_ID_BS_RVP ||
       PlatformInfo->BoardId == BOARD_ID_MINNOW2 ||
+      PlatformInfo->BoardId == BOARD_ID_MINNOW2_COMPATIBLE||
       PlatformInfo->BoardId == BOARD_ID_CVH) {
     ConfigureLpssAndSccGpio(&SystemConfiguration, PlatformInfo);
 

diff --git a/Vlv2TbltDevicePkg/PlatformPei/Platform.c b/Vlv2TbltDevicePkg/PlatformPei/Platform.c
@@ -192,6 +192,57 @@ PeiSmbusExec (
   );
 
 
+/**
+
+  Detemine compatible board 
+  @return 0: Not compatible board
+          1: Compatible board 
+
+**/
+UINT32 
+DetermineCompatibleBoard (
+  void
+  )
+{
+  UINTN PciD31F0RegBase = 0;
+  UINT32 GpioValue = 0;
+  UINT32 TmpVal = 0;
+  UINT32 MmioConf0 = 0;
+  UINT32 MmioPadval = 0;
+  UINT32 PConf0Offset = 0x200; //GPIO_S5_4 pad_conf0 register offset
+  UINT32 PValueOffset = 0x208; //GPIO_S5_4 pad_value register offset
+  UINT32 SSUSOffset = 0x2000;
+  UINT32 IoBase = 0;
+
+  DEBUG ((EFI_D_ERROR, "DetermineCompatibleBoard() Entry\n"));
+  PciD31F0RegBase = MmPciAddress (0,
+                      0,
+                      PCI_DEVICE_NUMBER_PCH_LPC,
+                      PCI_FUNCTION_NUMBER_PCH_LPC,
+                      0
+                    );
+  IoBase = MmioRead32 (PciD31F0RegBase + R_PCH_LPC_IO_BASE) & B_PCH_LPC_IO_BASE_BAR;
+
+  MmioConf0 = IoBase + SSUSOffset + PConf0Offset;
+  MmioPadval = IoBase + SSUSOffset + PValueOffset;
+  //0xFED0E200/0xFED0E208 is pad_Conf/pad_val register address of GPIO_S5_4
+  DEBUG ((EFI_D_ERROR, "MmioConf0[0x%x], MmioPadval[0x%x]\n", MmioConf0, MmioPadval));
+
+  MmioWrite32 (MmioConf0, 0x2003CC00);  
+
+  TmpVal = MmioRead32 (MmioPadval);
+  TmpVal &= ~0x6; //Clear bit 1:2
+  TmpVal |= 0x2; // Set the pin as GPI
+  MmioWrite32 (MmioPadval, TmpVal); 
+
+  GpioValue = MmioRead32 (MmioPadval);
+
+  DEBUG ((EFI_D_ERROR, "Gpio_S5_4 value is 0x%x\n", GpioValue));
+  return (GpioValue & 0x1);
+}
+
+
+
 EFI_STATUS
 FtpmPolicyInit (
   IN CONST EFI_PEI_SERVICES             **PeiServices,
@@ -854,6 +905,7 @@ ReadPlatformIds (
     UINTN                           DataSize;
     EFI_PLATFORM_INFO_HOB           TmpHob;
     EFI_PEI_READ_ONLY_VARIABLE2_PPI *PeiVar;
+    UINT32                          CompatibleBoard = 0; 
 
     Status = (**PeiServices).LocatePpi (
                                PeiServices,
@@ -882,9 +934,15 @@ ReadPlatformIds (
       return Status;
     }
 
-
-    PlatformInfoHob->BoardId    = BOARD_ID_MINNOW2;
-    DEBUG ((EFI_D_INFO,  "I'm Minnow2!\n"));
+    CompatibleBoard = DetermineCompatibleBoard();
+   if (1 == CompatibleBoard) {
+     PlatformInfoHob->BoardId    = BOARD_ID_MINNOW2_COMPATIBLE;
+     DEBUG ((EFI_D_INFO,  "I'm MinnowBoard Compatible!\n"));
+   } else {       
+     PlatformInfoHob->BoardId    = BOARD_ID_MINNOW2;
+     DEBUG ((EFI_D_INFO,  "I'm MinnowBoard Max!\n"));
+   }
+
 
     PlatformInfoHob->MemCfgID   = 0;
     PlatformInfoHob->BoardRev   = FabId + 1;	// FabId = 0 means FAB1 (BoardRev = 1), FabId = 1 means FAB2 (BoardRev = 2)...

diff --git a/Vlv2TbltDevicePkg/PlatformSetupDxe/Thermal.vfi b/Vlv2TbltDevicePkg/PlatformSetupDxe/Thermal.vfi
@@ -33,7 +33,26 @@ form formid = THERMAL_FORM_ID,
   title  = STRING_TOKEN(STR_THERMAL_TITLE);
 
   subtitle text = STRING_TOKEN(STR_THERMAL_CONFIGURATION);
-
+  oneof   varid   = Setup.CriticalThermalTripPoint,
+    prompt      = STRING_TOKEN(STR_ACPI_CRITICAL_THERMAL_TRIP_POINT),
+    help        = STRING_TOKEN(STR_ACPI_CRITICAL_THERMAL_TRIP_POINT_HELP),
+    option text = STRING_TOKEN (STR_85_C), value = 85, flags=0 | RESET_REQUIRED;     
+    option text = STRING_TOKEN (STR_87_C), value = 87, flags=0 | RESET_REQUIRED; 
+    option text = STRING_TOKEN (STR_90_C), value = 90, flags=0 | RESET_REQUIRED;
+    option text = STRING_TOKEN (STR_105_C), value = 105, flags=0 | RESET_REQUIRED;
+    option text = STRING_TOKEN (STR_110_C), value = 110, flags=0 | RESET_REQUIRED;
+    option text = STRING_TOKEN (STR_200_C), value = 200, flags=DEFAULT | MANUFACTURING | RESET_REQUIRED;
+  endoneof; 
+  oneof   varid   = Setup.PassiveThermalTripPoint,
+    prompt      = STRING_TOKEN (STR_ACPI_PASSIVE_THERMAL_TRIP_POINT),
+    help        = STRING_TOKEN (STR_ACPI_PASSIVE_THERMAL_TRIP_POINT_HELP),
+    option text = STRING_TOKEN (STR_85_C), value = 85, flags=0 | RESET_REQUIRED;
+    option text = STRING_TOKEN (STR_87_C), value = 87, flags=0 | RESET_REQUIRED;   
+    option text = STRING_TOKEN (STR_90_C), value = 90, flags=0 | RESET_REQUIRED;
+    option text = STRING_TOKEN (STR_100_C), value = 100, flags=0 | RESET_REQUIRED;
+    option text = STRING_TOKEN (STR_105_C), value = 105, flags=0 | RESET_REQUIRED;
+    option text = STRING_TOKEN (STR_180_C), value = 180, flags=DEFAULT | MANUFACTURING | RESET_REQUIRED;
+  endoneof;
 
   suppressif TRUE;
     numeric varid = Setup.PassiveTc1Value,

diff --git a/Vlv2TbltDevicePkg/PlatformSetupDxe/Vfr.vfr b/Vlv2TbltDevicePkg/PlatformSetupDxe/Vfr.vfr
@@ -21,6 +21,8 @@ formset
   guid     = SYSTEM_CONFIGURATION_GUID,
   title    = STRING_TOKEN(STR_SYSTEM_SETUP_TITLE),
   help     = STRING_TOKEN(STR_SYSTEM_SETUP_HELP),
+  class    = 1,
+  subclass = 0,
 
 
   varstore SYSTEM_CONFIGURATION, name = Setup, guid = SYSTEM_CONFIGURATION_GUID;

diff --git a/Vlv2TbltDevicePkg/PlatformSetupDxe/VfrStrings.uni b/Vlv2TbltDevicePkg/PlatformSetupDxe/VfrStrings.uni
diff --git a/Vlv2TbltDevicePkg/SaveMemoryConfig/SaveMemoryConfig.c b/Vlv2TbltDevicePkg/SaveMemoryConfig/SaveMemoryConfig.c
@@ -123,7 +123,7 @@ SaveMemoryConfigEntryPoint (
       MemInfoProtocol->MemInfoData.memSize  = 0;
       for (Channel = 0; Channel < CH_NUM; Channel ++){
         for (Slot = 0; Slot < DIMM_NUM; Slot ++){               
-          MemInfoProtocol->MemInfoData.dimmSize[Slot + (Channel * DIMM_NUM)] = PlatformInfoHobPtr->MemData.DimmSize[Slot];
+          MemInfoProtocol->MemInfoData.dimmSize[Slot + (Channel * DIMM_NUM)] = PlatformInfoHobPtr->MemData.DimmSize[Slot + (Channel * DIMM_NUM)];
         }
       }
   	  MemInfoProtocol->MemInfoData.memSize       = PlatformInfoHobPtr->MemData.MemSize;