Small footprint and configurable DRAM core

电路仿真

My notes for DDR3 SDRAM controller

HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.

Yosys Open SYnthesis Suite

IEEE P1735 decryptor for VHDL

A modern and open-source cross-platform software for chips reverse engineering.

Reverse-engineering tools for FPGA bitstreams, Altera and Xilinx

A DDR3 memory controller in Verilog for various FPGAs

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

Arduino Library for programming MachXO2/XO3 devices