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  1. RISC-V-Instruction-Set-Manual RISC-V-Instruction-Set-Manual Public

    Forked from riscv/riscv-isa-manual

    RISC-V Instruction Set Manual

    TeX

  2. RISC-V-Debug-Specification RISC-V-Debug-Specification Public

    Forked from riscv/riscv-debug-spec

    RISC-V Debug Specification

    Python

  3. RISC-V-Documentation-Resources RISC-V-Documentation-Resources Public

    Forked from riscv/docs-resources

    RISC-V Documentation Resources

  4. RISC-V-Performance-Events-Specification RISC-V-Performance-Events-Specification Public

    Forked from riscv/riscv-performance-events

    RISC-V Performance Events Specification

    Makefile

  5. RISC-V-Opcodes RISC-V-Opcodes Public

    Forked from riscv/riscv-opcodes

    RISC-V Opcodes

    Python

  6. RISC-V-Architecture-Profiles RISC-V-Architecture-Profiles Public

    Forked from riscv/riscv-profiles

    RISC-V Architecture Profiles

    Makefile

Repositories

Showing 10 of 87 repositories
  • PeakRDL-IPXACT Public Forked from SystemRDL/PeakRDL-ipxact

    Import and Export IP-XACT XML Register Models

    R-EAjks/PeakRDL-IPXACT’s past year of commit activity
    Python 0 GPL-3.0 14 0 0 Updated Oct 15, 2024
  • FuseSoC Public Forked from olofk/fusesoc

    Package Manager and Build Abstraction Tool for FPGA/ASIC Development

    R-EAjks/FuseSoC’s past year of commit activity
    Python 0 BSD-2-Clause 260 0 0 Updated Oct 7, 2024
  • R-EAjks/VeeR-EL2-RISC-V-Core’s past year of commit activity
    SystemVerilog 0 Apache-2.0 76 0 0 Updated Sep 19, 2024
  • VexRiscV Public Forked from SpinalHDL/VexRiscv

    An FPGA Friendly 32-Bit RISC-V CPU Implementation

    R-EAjks/VexRiscV’s past year of commit activity
    Assembly 0 MIT 427 0 0 Updated Sep 19, 2024
  • NEORV32-RISC-V-Processor Public Forked from stnolting/neorv32

    32-Bit RISC-V Soft-Core CPU

    R-EAjks/NEORV32-RISC-V-Processor’s past year of commit activity
    VHDL 0 BSD-3-Clause 235 0 0 Updated Sep 19, 2024
  • FlooNoC Public Forked from pulp-platform/FlooNoC

    A Fast, Low-Overhead On-chip Network

    R-EAjks/FlooNoC’s past year of commit activity
    SystemVerilog 0 Apache-2.0 23 0 0 Updated Sep 19, 2024
  • CORE-V-CVA6-RISC-V-CPU Public Forked from openhwgroup/cva6

    Application Class 6-Stage RISC-V CPU Capable of Booting Linux

    R-EAjks/CORE-V-CVA6-RISC-V-CPU’s past year of commit activity
    Assembly 0 708 0 0 Updated Sep 19, 2024
  • Cheshire Public Forked from pulp-platform/cheshire

    A Minimal Linux-Capable 64-Bit RISC-V SoC Built Around CVA6

    R-EAjks/Cheshire’s past year of commit activity
    Verilog 0 50 0 0 Updated Sep 19, 2024
  • PULP-Ara Public Forked from pulp-platform/ara

    A 64-Bit Vector Unit, Compatible With the RISC-V Vector Extension Version 1.0, Working as a Coprocessor to CORE-V's CVA6 Core

    R-EAjks/PULP-Ara’s past year of commit activity
    C 0 132 0 0 Updated Sep 19, 2024
  • Spatz Public Forked from pulp-platform/spatz

    Spatz is a Compact RISC-V-Based Vector Processor Meant for High-Performance, Small Computing Clusters

    R-EAjks/Spatz’s past year of commit activity
    C 0 Apache-2.0 18 0 0 Updated Sep 19, 2024

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