RISCVNexus
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picorv32
picorv32 PublicForked from YosysHQ/picorv32
PicoRV32 - A Size-Optimized RISC-V CPU
Verilog 1
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softvector
softvector PublicForked from tum-ei-eda/softvector
Vector arithmetic library targeting simulation of Vector Processing Units (VPUs) for various targets, e.g., ETISS.
C++
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muriscv-nn
muriscv-nn PublicForked from tum-ei-eda/muriscv-nn
muRISCV-NN is a collection of efficient deep learning kernels for embedded platforms and microcontrollers.
C++
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pyocdriscv32
pyocdriscv32 PublicForked from michg/pyocdriscv32
Python script for controlling the debug-jtag port of riscv cores
Verilog
Repositories
- riscv-gnu-toolchain Public Forked from riscv-collab/riscv-gnu-toolchain
GNU toolchain for RISC-V, including GCC
RISCVNexus/riscv-gnu-toolchain’s past year of commit activity - sifive-blis Public Forked from sifive/sifive-blis
BLAS-like Library Instantiation Software Framework
RISCVNexus/sifive-blis’s past year of commit activity - BRISKI Public Forked from riadhbenabdelhamid/BRISKI
BRISKI ( Barrel RISC-V for Kilo-core Implementations ) is a fast and compact RISC-V barrel processor core that emphasize high throughput and compute density to increase the amount of cores in many-core design without sacrificing performance.
RISCVNexus/BRISKI’s past year of commit activity
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