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an experiment in Verilog with the 16-bit LC3 architecture. I was thinking about multi-core processing and wanted to build something that would automatically balance the processing load from four input streams. I was inspired by a paper on “Neuro” Network-On-a-Chip by Thomas Ebi, Mohammad Al Faruque and Jörg Henkel.

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This project was developed by R. M. Keelan Downton as part of COSC121 at Georgetown University. The code combines his original work with some template code provided by Richard Squier who taught the course.

/docs draft design diagrams and final presentation

/lib an Electric .jelib file that is the main work of this project

/run a verilog deck output from the jelib and a sample results.txt file

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an experiment in Verilog with the 16-bit LC3 architecture. I was thinking about multi-core processing and wanted to build something that would automatically balance the processing load from four input streams. I was inspired by a paper on “Neuro” Network-On-a-Chip by Thomas Ebi, Mohammad Al Faruque and Jörg Henkel.

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