Fixed CPLD recovery logic edge case

Ryzee119 · Nov 8, 2019 · dc0b111 · dc0b111
1 parent 001f336
commit dc0b111
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Showing 4 changed files with 51 additions and 24 deletions.
diff --git a/Firmware/OpenXenium.xise b/Firmware/OpenXenium.xise
@@ -17,10 +17,10 @@
   <files>
     <file xil_pn:name="openxenium.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
     </file>
     <file xil_pn:name="openxenium.ucf" xil_pn:type="FILE_UCF">
-      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
   </files>
 
@@ -29,8 +29,8 @@
     <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
-    <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Autosignature Generation" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -40,7 +40,7 @@
     <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
     <property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Collapsing Input Limit (2-54)" xil_pn:value="54" xil_pn:valueState="default"/>
-    <property xil_pn:name="Collapsing Pterm Limit (1-90)" xil_pn:value="25" xil_pn:valueState="default"/>
+    <property xil_pn:name="Collapsing Pterm Limit (1-90)" xil_pn:value="50" xil_pn:valueState="default"/>
     <property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
@@ -77,7 +77,7 @@
     <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
     <property xil_pn:name="I/O Pin Termination" xil_pn:value="Keeper" xil_pn:valueState="default"/>
     <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Implementation Template" xil_pn:value="Optimize Balance" xil_pn:valueState="default"/>
+    <property xil_pn:name="Implementation Template" xil_pn:value="Optimize Speed" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|openxenium|Behavioral" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Implementation Top File" xil_pn:value="openxenium.vhd" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/openxenium" xil_pn:valueState="non-default"/>
@@ -100,14 +100,14 @@
     <property xil_pn:name="Logic Optimization" xil_pn:value="Speed" xil_pn:valueState="default"/>
     <property xil_pn:name="Macro Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Macrocell Power Setting" xil_pn:value="Std" xil_pn:valueState="default"/>
-    <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
     <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
     <property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
     <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
     <property xil_pn:name="Number of Clock Buffers" xil_pn:value="4" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Effort" xil_pn:value="High" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
     <property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
@@ -205,6 +205,7 @@
     <property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/>
     <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
     <property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="iMPACT Project File" xil_pn:value="OpenXenium.ipf" xil_pn:valueState="non-default"/>
     <!--                                                                                  -->
     <!-- The following properties are for internal use only. These should not be modified.-->
     <!--                                                                                  -->

diff --git a/Firmware/openxenium.ucf b/Firmware/openxenium.ucf
@@ -3,6 +3,10 @@
 NET "LPC_CLK" TNM_NET = LPC_CLK;
 TIMESPEC TS_LPC_CLK = PERIOD "LPC_CLK" 33 Mhz HIGH 50%;
 #PACE: Start of Constraints generated by PACE
+NET REG_00EF_WRITE(0) INIT=S;
+NET REG_00EF_WRITE(1) INIT=R;
+NET REG_00EF_WRITE(2) INIT=R;
+NET REG_00EF_WRITE(3) INIT=R;
 
 #PACE: Start of PACE I/O Pin Assignments
 NET "FLASH_ADDRESS<0>"  LOC = "P47"  ; 
@@ -44,7 +48,7 @@ NET "HEADER_LED_G"  LOC = "P11"  ;
 NET "HEADER_LED_R"  LOC = "P12"  ; 
 NET "HEADER_MOSI"  LOC = "P33"  ; 
 NET "HEADER_SCK"  LOC = "P32"  ; 
-NET "LPC_CLK"  LOC = "P17"  ; 
+NET "LPC_CLK"  LOC = "P17" | BUFG = CLK ; 
 NET "LPC_LAD<0>"  LOC = "P22" ; 
 NET "LPC_LAD<1>"  LOC = "P24" ; 
 NET "LPC_LAD<2>"  LOC = "P25" ; 

diff --git a/Firmware/openxenium.vhd b/Firmware/openxenium.vhd
@@ -150,7 +150,7 @@ ARCHITECTURE Behavioral OF openxenium IS
 
 BEGIN
    --ASSIGN THE IO TO SIGNALS BASED ON REQUIRED BEHAVIOUR
-   --HEADER_CS <= REG_00EF(5);
+   --HEADER_CS <= REG_00EF(5); Really need to put this back in somehow. 100% full :(
    HEADER_SCK <= REG_00EF_WRITE(6);
    HEADER_MOSI <= REG_00EF_WRITE(4);
 
@@ -182,7 +182,7 @@ BEGIN
                (LPC_CURRENT_STATE = TAR1 OR
                LPC_CURRENT_STATE = TAR2 OR
                LPC_CURRENT_STATE = SYNCING) ELSE '1';
-			   
+
    --Output Enable for Flash Memory Read (Active low)
    --Output Enable must be pulled low for 50ns before data is valid for reading
    FLASH_OE <= '0' WHEN CYCLE_TYPE = MEM_READ AND
@@ -193,7 +193,7 @@ BEGIN
                LPC_CURRENT_STATE = READ_DATA0 OR
                LPC_CURRENT_STATE = READ_DATA1 OR
                LPC_CURRENT_STATE = TAR_EXIT) ELSE '1';
-			   
+
    --D0 has the following behaviour
    --Held low on boot to ensure it boots from the LPC then released when definitely booting from modchip.
    --When soldered to LFRAME it will simulate LPC transaction aborts for 1.6.
@@ -207,22 +207,15 @@ BEGIN
 
    REG_00EF_READ <= XENIUM_RECOVERY & '0' & HEADER_4 & HEADER_1 & REG_00EF_WRITE(3 DOWNTO 0);
 
-   PROCESS (LPC_CLK, LPC_RST) BEGIN
+PROCESS (LPC_CLK, LPC_RST) BEGIN
 
    IF (LPC_RST = '0') THEN
-
       --LPC_RST goes low during boot up or hard reset.
-	  --We need to set D0 only if not TSOP booting.
+      --We need to set D0 only if not TSOP booting.
       D0LEVEL <= TSOPBOOT;
       LPC_CURRENT_STATE <= WAIT_START;
       CYCLE_TYPE <= IO_READ;
-
-      --If the recovery jumper is set, it will set the banking register to 
-      --Bank ten on boot forcing it to boot the recovery bios.
-      IF XENIUM_RECOVERY = '0' AND TSOPBOOT = '0' THEN
-         REG_00EF_WRITE(3 DOWNTO 0) <= "1010";
-      END IF;
-
+
    ELSIF (rising_edge(LPC_CLK)) THEN 
       CASE LPC_CURRENT_STATE IS
          WHEN WAIT_START => 
@@ -257,6 +250,10 @@ BEGIN
             ELSIF COUNT = 4 THEN
                LPC_ADDRESS(19 DOWNTO 16) <= LPC_LAD;
                --BANK CONTROL
+               -- Set recovery bank if switch is activated
+               IF XENIUM_RECOVERY = '0' AND TSOPBOOT = '0' AND D0LEVEL = '0' THEN
+                  REG_00EF_WRITE(3 DOWNTO 0) <= "1010";
+               END IF;
                CASE REG_00EF_WRITE(3 DOWNTO 0) IS
                   WHEN "0001" => 
                      LPC_ADDRESS(20 DOWNTO 18) <= "110"; --256kb bank
@@ -333,8 +330,8 @@ BEGIN
          WHEN TAR2 => 
             LPC_CURRENT_STATE <= SYNCING;
             COUNT <= 6;
-			
-		 --SYNCING STAGE
+            
+         --SYNCING STAGE
          WHEN SYNCING =>
             COUNT <= COUNT - 1;    
             --Buffer IO reads during syncing. Helps output timings

diff --git a/Hardware/Xenium2019_centroid.csv b/Hardware/Xenium2019_centroid.csv
@@ -0,0 +1,25 @@
+Screaming Circuits SMD component position file.
+Created by Centroid_ScreamingCircuits_smd.ulp 1.2.0.
+
+Centroid Data for pc board: "Xenium2019.brd" as of: 29/10/2019 9:48 PM
+Measurements are in inches. Comma delimited
+Only surface mount components included
+
+RefDes,Layer,LocationX,LocationY,Rotation
+C1,Top,0.890,0.470,270
+C2,Top,1.160,1.165,90
+C4,Top,1.160,0.990,270
+D0,Top,1.300,1.385,90
+J1,Top,0.565,0.215,0
+L1,Top,1.400,0.395,0
+Q1,Top,1.285,0.547,180
+Q2,Top,1.155,0.547,180
+Q3,Top,1.025,0.547,180
+Q4,Top,1.415,0.547,180
+R1,Top,1.025,0.393,90
+R2,Top,1.155,0.393,90
+R3,Top,1.285,0.393,90
+R5,Top,0.260,0.390,270
+TP1,Top,1.163,1.300,0
+U1,Top,0.575,0.575,0
+U2,Top,0.675,1.120,0