A VHDL project proposing an implementation of a hardware oriented reservoir computer on FPGA’s to create a crypto-chaotic communication channel
This research paper proposes a hardware-oriented Reservoir Computer topology called Cyclic Reservoir that is able to achieve close to state-of-the-art performance for chaotic time series prediction. A hardware implementation targeting FPGAs using Stochastic Computing elements is then proposed that is able to substantially reduce the hardware resource demand of the network and avails of a high robustness to environmental noise. A chaotic communication channel using the hardware implementation of the Reservoir Computer is proposed that is more secure than analog chaotic circuit communication channels and plausibly more efficient in real-world use than other Artificial Neural Network based chaotic communication channels.