Add information about the analog comparators ACMP and AORC

docs/memory_map.txt

@@ -52,13 +52,14 @@
         CLKCR, PWRSVCR, CGATSTAT0, CGATSET0, CGATCLR0, OSCCSR
       0x40010400 - 0x400104FF RCU Reset Control Unit
         RSTSTAT, RSTSET, RSTCLR, RSTCON
-      0x40010500 - 0x400105FF Reserved
+      0x40010500 - 0x400105FF Reserved (ACMP ORC)
       0x40010600 - 0x400106FF ERU
         EXISEL, EXICON0-3, EXOCON0-3
       0x40010700 - 0x400109FF Reserved
       0x40010A00 - 0x40010AFF RTC
         ID, CTR, RAWSTAT, STSSR, MSKSR, CLRSR, ATIM0, ATIM1, TIM0, TIM1
       0x40010B00 - 0x40010FFF Reserved
+      0x4001105c - 0x40011067 ANACMPx
       0x40011000 - 0x4001107F ANACTRL Analog Control (cause AHB/APB access)
         ANAVDEL, ANAOFFSET
       0x40011080 - 0x4001FFFF Reserved

src/peripherals/acmp.h

@@ -0,0 +1,112 @@
+// Support for the XMC1x00 ACMP (analog comparator)
+//
+// XMC1200 ACMP pin connections:
+// Analog inputs:
+//   P2.1:            ACMP2.INP
+//   P2.2:  ORC0.AIN  ACMP2.INN
+//   P2.3:  ORC1.AIN
+//   P2.4:  ORC2.AIN
+//   P2.5:  ORC3.AIN
+//   P2.6:  ORC4.AIN  ACMP1.INN
+//   P2.7:  ORC5.AIN  ACMP1.INP
+//   P2.8:  ORC6.AIN  ACMP0.INN
+//   P2.9:  ORC7.AIN  ACMP0.INP
+//   P2.11:           ACMP.REF
+// ORC outputs:
+//   ACMP0.OUT: P0.10 alt4              P2.10 alt6  ERU0.0A0  BCCU0.IN5
+//   ACMP1.OUT:             P1.0 alt 6  P2.5pull    ERU0.1A0  BCCU0.IN0
+//   ACMP2.OUT: P0.5 alt 6  P1.2 alt 6  P2.3pull    ERU0.2A0  BCCU0.IN3
+//   ORC0.OUT:  ERU0.0B2
+//   ORC1.OUT:  ERU0.1B2
+//   ORC2.OUT:  ERU0.0A2 ERU0.2B2
+//   ORC3.OUT:  ERU0.1A2
+//   ORC4.OUT:  ERU0.2A2
+//   ORC5.OUT:  ERU0.3A2
+//   ORC6.OUT:  ERU0.3B2
+//   ORC7.OUT:  ERU0.3A0
+//
+// Interrupts are enabled through setting SCU_* bits in SCU_SRMSK
+
+#ifndef PERIPHERALS_ACMP_H
+#define PERIPHERALS_ACMP_H
+
+#define ACMP_ORCCTRL    REGISTER_32(ORC_BASE)
+#define ACMP_ANACMP(x)  REGISTER_32(ACMP_BASE + (x * 4))
+
+unsigned int acmpEnable(void) {}
+unsigned int acmpDisable(void) {}
+// Configure the out of range comparators.
+//   enable is a bitwise or of the desired ORC_ENORCx + ORC_CNFx flags.
+//   ORC_CNFx sets the trigger on the rising edge (falling edge is default).
+void orcConfigure(unsigned int enable) { ACMP_ORCCTRL = enable; }
+// Configure an analog comparator.
+//   channel is the comparator channel (0 through 2).
+//   flags is a bitwise or of the desired ACMP_ flags.
+void acmpConfigure(unsigned int channel, unsigned int flags) {
+	ACMP_ANACMP(channel) = flags;
+}
+// Read the analog comparator channel result.
+bool acmpRead(unsigned int channel) {
+	return ACMP_ANACMP(channel) & ACMP_CMP_OUT;
+}
+
+// Out of range comparator enable flags
+#define ORC_ENORC0 BIT0
+#define ORC_ENORC1 BIT1
+#define ORC_ENORC2 BIT2
+#define ORC_ENORC3 BIT3
+#define ORC_ENORC4 BIT4
+#define ORC_ENORC5 BIT5
+#define ORC_ENORC6 BIT6
+#define ORC_ENORC7 BIT7
+// Out of range comparator rising edge select
+// (falling edge is default)
+#define ORC_CNF0 BIT16
+#define ORC_CNF1 BIT17
+#define ORC_CNF2 BIT18
+#define ORC_CNF3 BIT19
+#define ORC_CNF4 BIT20
+#define ORC_CNF5 BIT21
+#define ORC_CNF6 BIT22
+#define ORC_CNF7 BIT23
+
+// Analog comparator flags
+// enable
+#define ACMP_CMP_EN           BIT0
+// disable filter
+#define ACMP_CMP_FLT_OFF      BIT1
+// invert output
+#define ACMP_CMP_INV_OUT      BIT3
+// select mV of hysteresis
+#define ACMP_CMP_HYST_ADJ_0   0
+#define ACMP_CMP_HYST_ADJ_10  BIT4
+#define ACMP_CMP_HYST_ADJ_15  BIT5
+#define ACMP_CMP_HYST_ADJ_20  BIT5 | BIT4
+// ref voltage from resistor divider is applied to ACMP1
+#define ACMP_CMP1_DIV_EN      BIT6
+// connect ACMP1.INP to ACMP0.INN or ACMP2.INP
+// used to supply ref voltage to both pins
+#define ACMP_CMP0_SEL         BIT6
+#define ACMP_CMP2_SEL         BIT6
+// enable low power mode for all comparators
+// default is high power mode for better performance.
+#define ACMP_CMP0_LPWR        BIT8
+// output monitor bit (read only)
+// Vminus > Vplus: 0
+// Vminus < Vplus: 1
+#define ACMP_CMP_OUT          BIT15
+
+// Interrupts are enabled through setting SCU_* bits in SCU_SRMSK
+#define SCU_ACMP0I  BIT4
+#define SCU_ACMP1I  BIT5
+#define SCU_ACMP2I  BIT6
+#define SCU_ORC0I   BIT8
+#define SCU_ORC1I   BIT9
+#define SCU_ORC2I   BIT10
+#define SCU_ORC3I   BIT11
+#define SCU_ORC4I   BIT12
+#define SCU_ORC5I   BIT13
+#define SCU_ORC6I   BIT14
+#define SCU_ORC7I   BIT15
+
+#endif

src/peripherals/rtc.c

@@ -16,6 +16,11 @@ unsigned int rtcEnable(const unsigned int year,
                        const unsigned int hour,
                        const unsigned int minute,
                        const unsigned int second) {
+	// Available clock sources selected by SCU_CLKCR.RTCCLKSEL are:
+	// DCO2 standby clock (default)
+	// ERU0 IOUT0
+	// ACMPx OUT (3 sources) (not present in the XMC1100)
+
 	// Ungate the RTC clock.
 	scuUngatePeripheralClock(CGATCLR0_RTC);
 
@@ -24,17 +29,8 @@ unsigned int rtcEnable(const unsigned int year,
 		return 1;
 	}
 
-	// Set the start time.
-	rtcSetDateTime(year, month, day, hour, minute, second);
-
-	// RTC is in reset after power up until reset is released.
-	// 0x7fff:  prescaler (32768Hz clock/0x7fff = 1 update/second).
-	// SUS BIT1: 0: Module is not suspended during debug
-	// ENB BIT0: 1: Enable module
-	WAIT_FOR_SERIAL;
-	RTC_CTR = (0x7fff << 16) | BIT0;
-
-	return 0;
+	// Set the time and start the clock.
+	return rtcSetDateTime(year, month, day, hour, minute, second);
 }
 
 unsigned int rtcDisable(void) {
@@ -49,10 +45,20 @@ unsigned int rtcSetDateTime(const unsigned int year,
                             const unsigned int hour,
                             const unsigned int minute,
                             const unsigned int second) {
+	// Time values can only be written when RTC is disabled.
+	rtcDisable();
+
 	// Program TIM0 then TIM1
 	WAIT_FOR_SERIAL;
 	RTC_TIM0 = TIME0(day, hour, minute, second);
 	RTC_TIM1 = TIME1(year, month);
+
+	// 0x7fff:  prescaler (32768Hz clock/0x7fff = 1 update/second).
+	// SUS BIT1: 0: Module is not suspended during debug
+	// ENB BIT0: 1: Enable module
+	WAIT_FOR_SERIAL;
+	RTC_CTR = (0x7fff << 16) | BIT0;
+
 	return 0;
 }
 

src/peripherals/rtc.h

@@ -44,4 +44,17 @@ unsigned int rtcClearAlarm(void);
                      MSKSR_MPMI | MSKSR_MPSE)
 #define MSKSR_MAI  BIT8
 
+// Interrupts are enabled through setting SCU_* bits in SCU_SRMSK
+// CTR mirror register updated
+#define SCU_RTC_CTR    BIT24
+// ATIM0 mirror register updated
+#define SCU_RTC_ATIM0  BIT25
+// ATIM1 mirror register updated
+#define SCU_RTC_ATIM1  BIT26
+// TIM0 mirror register updated
+#define SCU_RTC_TIM0   BIT27
+// TIM1 mirror register updated
+#define SCU_RTC_TIM1   BIT28
+
+
 #endif

src/xmc1100.h

@@ -62,6 +62,8 @@
 #define SCS_BASE		0xe000ed00
 #define STK_BASE		0xe000e010
 #define WDT_BASE 		0x40020000
+#define ORC_BASE 		0x40010500
+#define ACMP_BASE 		0x4001105c
 #define RTC_BASE 		0x40010a00
 #define SCU_BASE 		0x40010000
 #define TSE_BASE		0x40010000