Testing

Assign_4_2/Assign_4_2.cache/wt/gui_handlers.wdf

@@ -1,32 +1,32 @@
 version:1
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@@ -36,4 +36,4 @@ version:1
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-eof:4277440480
+eof:2901389036

Assign_4_2/Assign_4_2.cache/wt/java_command_handlers.wdf

@@ -1,13 +1,14 @@
 version:1
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Assign_4_2/Assign_4_2.cache/wt/project.wpc

@@ -1,3 +1,3 @@
 version:1
-6d6f64655f636f756e7465727c4755494d6f6465:3
+6d6f64655f636f756e7465727c4755494d6f6465:4
 eof:

Assign_4_2/Assign_4_2.cache/wt/webtalk_pa.xml

@@ -3,7 +3,7 @@
 <!--The data in this file is primarily intended for consumption by Xilinx tools.
 The structure and the elements are likely to change over the next few releases.
 This means code written to parse this file will need to be revisited each subsequent release.-->
-<application name="pa" timeStamp="Fri Oct 25 10:32:22 2019">
+<application name="pa" timeStamp="Sun Oct 27 08:40:33 2019">
 <section name="Project Information" visible="false">
 <property name="ProjectID" value="61ea9ef177e7492aaeb814396f3ad3cb" type="ProjectID"/>
 <property name="ProjectIteration" value="1" type="ProjectIteration"/>
@@ -19,10 +19,11 @@ This means code written to parse this file will need to be revisited each subseq
 <item name="Java Command Handlers">
 <property name="AddSources" value="1" type="JavaHandler"/>
 <property name="CloseProject" value="2" type="JavaHandler"/>
+<property name="SaveFileProxyHandler" value="1" type="JavaHandler"/>
 <property name="SimulationBreak" value="2" type="JavaHandler"/>
-<property name="SimulationRelaunch" value="16" type="JavaHandler"/>
+<property name="SimulationRelaunch" value="17" type="JavaHandler"/>
 <property name="SimulationRestart" value="6" type="JavaHandler"/>
-<property name="SimulationRun" value="10" type="JavaHandler"/>
+<property name="SimulationRun" value="11" type="JavaHandler"/>
 <property name="SimulationRunAll" value="26" type="JavaHandler"/>
 <property name="SimulationRunForTime" value="138" type="JavaHandler"/>
 <property name="SimulationStep" value="11" type="JavaHandler"/>
@@ -32,32 +33,32 @@ This means code written to parse this file will need to be revisited each subseq
 <item name="Gui Handlers">
 <property name="AbstractCombinedPanel_REMOVE_SELECTED_ELEMENTS" value="1" type="GuiHandlerData"/>
 <property name="AddSrcWizard_SPECIFY_SIMULATION_SPECIFIC_HDL_FILES" value="1" type="GuiHandlerData"/>
-<property name="BaseDialog_OK" value="21" type="GuiHandlerData"/>
+<property name="BaseDialog_OK" value="22" type="GuiHandlerData"/>
 <property name="CreateSrcFileDialog_FILE_NAME" value="1" type="GuiHandlerData"/>
 <property name="DefineModulesDialog_DEFINE_MODULES_AND_SPECIFY_IO_PORTS" value="1" type="GuiHandlerData"/>
-<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="12" type="GuiHandlerData"/>
-<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="20" type="GuiHandlerData"/>
-<property name="GraphicalView_ZOOM_FIT" value="67" type="GuiHandlerData"/>
-<property name="GraphicalView_ZOOM_IN" value="29" type="GuiHandlerData"/>
-<property name="GraphicalView_ZOOM_OUT" value="11" type="GuiHandlerData"/>
+<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="17" type="GuiHandlerData"/>
+<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="22" type="GuiHandlerData"/>
+<property name="GraphicalView_ZOOM_FIT" value="69" type="GuiHandlerData"/>
+<property name="GraphicalView_ZOOM_IN" value="34" type="GuiHandlerData"/>
+<property name="GraphicalView_ZOOM_OUT" value="15" type="GuiHandlerData"/>
 <property name="HCodeEditor_CLOSE" value="1" type="GuiHandlerData"/>
 <property name="PACommandNames_ADD_SOURCES" value="1" type="GuiHandlerData"/>
 <property name="PACommandNames_SIMULATION_LIVE_BREAK" value="2" type="GuiHandlerData"/>
 <property name="PACommandNames_SIMULATION_LIVE_RESTART" value="6" type="GuiHandlerData"/>
 <property name="PACommandNames_SIMULATION_LIVE_RUN" value="146" type="GuiHandlerData"/>
 <property name="PACommandNames_SIMULATION_LIVE_RUN_ALL" value="26" type="GuiHandlerData"/>
 <property name="PACommandNames_SIMULATION_LIVE_STEP" value="11" type="GuiHandlerData"/>
-<property name="PACommandNames_SIMULATION_RELAUNCH" value="19" type="GuiHandlerData"/>
-<property name="PACommandNames_SIMULATION_RUN_BEHAVIORAL" value="10" type="GuiHandlerData"/>
+<property name="PACommandNames_SIMULATION_RELAUNCH" value="20" type="GuiHandlerData"/>
+<property name="PACommandNames_SIMULATION_RUN_BEHAVIORAL" value="11" type="GuiHandlerData"/>
 <property name="PAViews_CODE" value="1" type="GuiHandlerData"/>
 <property name="ProgressDialog_BACKGROUND" value="1" type="GuiHandlerData"/>
 <property name="ProjectTab_RELOAD" value="5" type="GuiHandlerData"/>
 <property name="RDICommands_WAVEFORM_SAVE_CONFIGURATION" value="1" type="GuiHandlerData"/>
-<property name="RDIViews_WAVEFORM_VIEWER" value="145" type="GuiHandlerData"/>
+<property name="RDIViews_WAVEFORM_VIEWER" value="151" type="GuiHandlerData"/>
 <property name="SimulationLiveRunForComp_SPECIFY_TIME_AND_UNITS" value="1" type="GuiHandlerData"/>
 <property name="SrcChooserPanel_CREATE_FILE" value="1" type="GuiHandlerData"/>
-<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="3" type="GuiHandlerData"/>
-<property name="TaskBanner_CLOSE" value="17" type="GuiHandlerData"/>
+<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="5" type="GuiHandlerData"/>
+<property name="TaskBanner_CLOSE" value="18" type="GuiHandlerData"/>
 <property name="WaveformNameTree_WAVEFORM_NAME_TREE" value="10" type="GuiHandlerData"/>
 <property name="WaveformView_ADD_MARKER" value="2" type="GuiHandlerData"/>
 <property name="WaveformView_GOTO_CURSOR" value="2" type="GuiHandlerData"/>
@@ -69,9 +70,9 @@ This means code written to parse this file will need to be revisited each subseq
 <property name="WaveformView_PREVIOUS_TRANSITION" value="2" type="GuiHandlerData"/>
 </item>
 <item name="Other">
-<property name="GuiMode" value="27" type="GuiMode"/>
+<property name="GuiMode" value="33" type="GuiMode"/>
 <property name="BatchMode" value="0" type="BatchMode"/>
-<property name="TclMode" value="22" type="TclMode"/>
+<property name="TclMode" value="28" type="TclMode"/>
 </item>
 </section>
 </application>

Assign_4_2/Assign_4_2.cache/wt/xsim.wdf

@@ -1,4 +1,4 @@
 version:1
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-eof:241934075
+eof:2427094519

Assign_4_2/Assign_4_2.sim/sim_1/behav/xsim/compile.bat

@@ -6,7 +6,7 @@ REM Filename    : compile.bat
 REM Simulator   : Xilinx Vivado Simulator
 REM Description : Script for compiling the simulation design source files
 REM
-REM Generated by Vivado on Fri Oct 25 10:09:07 +0500 2019
+REM Generated by Vivado on Sun Oct 27 08:19:37 +0500 2019
 REM SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
 REM
 REM Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

Assign_4_2/Assign_4_2.sim/sim_1/behav/xsim/compile.log

@@ -1,5 +1,5 @@
 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Sanaullah/Documents/GitHub/Verilog/Assign_4_2/Assign_4_2.srcs/sources_1/new/FSM_1101.v" into library xil_defaultlib
 INFO: [VRFC 10-311] analyzing module FSM_1101
-WARNING: [VRFC 10-756] identifier State0 is used before its declaration [C:/Users/Sanaullah/Documents/GitHub/Verilog/Assign_4_2/Assign_4_2.srcs/sources_1/new/FSM_1101.v:32]
 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Sanaullah/Documents/GitHub/Verilog/Assign_4_2/Assign_4_2.srcs/sim_1/new/testbench.v" into library xil_defaultlib
 INFO: [VRFC 10-311] analyzing module testbench
+WARNING: [VRFC 10-986] literal value truncated to fit in 36 bits [C:/Users/Sanaullah/Documents/GitHub/Verilog/Assign_4_2/Assign_4_2.srcs/sim_1/new/testbench.v:37]

Assign_4_2/Assign_4_2.sim/sim_1/behav/xsim/elaborate.bat

@@ -6,7 +6,7 @@ REM Filename    : elaborate.bat
 REM Simulator   : Xilinx Vivado Simulator
 REM Description : Script for elaborating the compiled design
 REM
-REM Generated by Vivado on Fri Oct 25 10:09:08 +0500 2019
+REM Generated by Vivado on Sun Oct 27 08:19:38 +0500 2019
 REM SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
 REM
 REM Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

Assign_4_2/Assign_4_2.sim/sim_1/behav/xsim/simulate.bat

@@ -6,7 +6,7 @@ REM Filename    : simulate.bat
 REM Simulator   : Xilinx Vivado Simulator
 REM Description : Script for simulating the design by launching the simulator
 REM
-REM Generated by Vivado on Fri Oct 25 10:09:09 +0500 2019
+REM Generated by Vivado on Sun Oct 27 07:00:12 +0500 2019
 REM SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
 REM
 REM Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

Assign_4_2/Assign_4_2.sim/sim_1/behav/xsim/webtalk.jou

@@ -2,8 +2,8 @@
 # Webtalk v2017.4 (64-bit)
 # SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
 # IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
-# Start of session at: Thu Oct 24 10:33:50 2019
-# Process ID: 8720
+# Start of session at: Sun Oct 27 08:19:27 2019
+# Process ID: 3756
 # Current directory: C:/Users/Sanaullah/Documents/GitHub/Verilog/Assign_4_2/Assign_4_2.sim/sim_1/behav/xsim
 # Command line: wbtcv.exe -mode batch -source C:/Users/Sanaullah/Documents/GitHub/Verilog/Assign_4_2/Assign_4_2.sim/sim_1/behav/xsim/xsim.dir/testbench_behav/webtalk/xsim_webtalk.tcl -notrace
 # Log file: C:/Users/Sanaullah/Documents/GitHub/Verilog/Assign_4_2/Assign_4_2.sim/sim_1/behav/xsim/webtalk.log

Assign_4_2/Assign_4_2.sim/sim_1/behav/xsim/webtalk.log

@@ -2,12 +2,14 @@
 # Webtalk v2017.4 (64-bit)
 # SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
 # IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
-# Start of session at: Thu Oct 24 10:33:50 2019
-# Process ID: 8720
+# Start of session at: Sun Oct 27 08:19:27 2019
+# Process ID: 3756
 # Current directory: C:/Users/Sanaullah/Documents/GitHub/Verilog/Assign_4_2/Assign_4_2.sim/sim_1/behav/xsim
 # Command line: wbtcv.exe -mode batch -source C:/Users/Sanaullah/Documents/GitHub/Verilog/Assign_4_2/Assign_4_2.sim/sim_1/behav/xsim/xsim.dir/testbench_behav/webtalk/xsim_webtalk.tcl -notrace
 # Log file: C:/Users/Sanaullah/Documents/GitHub/Verilog/Assign_4_2/Assign_4_2.sim/sim_1/behav/xsim/webtalk.log
 # Journal file: C:/Users/Sanaullah/Documents/GitHub/Verilog/Assign_4_2/Assign_4_2.sim/sim_1/behav/xsim\webtalk.jou
 #-----------------------------------------------------------
 source C:/Users/Sanaullah/Documents/GitHub/Verilog/Assign_4_2/Assign_4_2.sim/sim_1/behav/xsim/xsim.dir/testbench_behav/webtalk/xsim_webtalk.tcl -notrace
-INFO: [Common 17-206] Exiting Webtalk at Thu Oct 24 10:33:51 2019...
+INFO: [Common 17-186] 'C:/Users/Sanaullah/Documents/GitHub/Verilog/Assign_4_2/Assign_4_2.sim/sim_1/behav/xsim/xsim.dir/testbench_behav/webtalk/usage_statistics_ext_xsim.xml' has been successfully sent to Xilinx on Sun Oct 27 08:19:36 2019. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/Vivado/2017.4/doc/webtalk_introduction.html.
+webtalk_transmit: Time (s): cpu = 00:00:00 ; elapsed = 00:00:08 . Memory (MB): peak = 52.133 ; gain = 0.727
+INFO: [Common 17-206] Exiting Webtalk at Sun Oct 27 08:19:36 2019...

Assign_4_2/Assign_4_2.sim/sim_1/behav/xsim/webtalk_10144.backup.jou

@@ -0,0 +1,12 @@
+#-----------------------------------------------------------
+# Webtalk v2017.4 (64-bit)
+# SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
+# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
+# Start of session at: Sun Oct 27 07:00:11 2019
+# Process ID: 10144
+# Current directory: C:/Users/Sanaullah/Documents/GitHub/Verilog/Assign_4_2/Assign_4_2.sim/sim_1/behav/xsim
+# Command line: wbtcv.exe -mode batch -source C:/Users/Sanaullah/Documents/GitHub/Verilog/Assign_4_2/Assign_4_2.sim/sim_1/behav/xsim/xsim.dir/testbench_behav/webtalk/xsim_webtalk.tcl -notrace
+# Log file: C:/Users/Sanaullah/Documents/GitHub/Verilog/Assign_4_2/Assign_4_2.sim/sim_1/behav/xsim/webtalk.log
+# Journal file: C:/Users/Sanaullah/Documents/GitHub/Verilog/Assign_4_2/Assign_4_2.sim/sim_1/behav/xsim\webtalk.jou
+#-----------------------------------------------------------
+source C:/Users/Sanaullah/Documents/GitHub/Verilog/Assign_4_2/Assign_4_2.sim/sim_1/behav/xsim/xsim.dir/testbench_behav/webtalk/xsim_webtalk.tcl -notrace