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analysis-model Public
Forked from jenkinsci/analysis-modelA library to read static analysis reports into a Java object model
Java MIT License UpdatedJun 13, 2024 -
chipyard Public
Forked from ucb-bar/chipyardAn Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
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chisel-release Public
Forked from ucb-bar/chisel-releaseChisel release tooling
BSD 3-Clause "New" or "Revised" License UpdatedApr 14, 2023 -
chisel-tutorial Public
Forked from ucb-bar/chisel-tutorialchisel tutorial exercises and answers
Scala Other UpdatedJan 6, 2022 -
cloudcomputing Public
Forked from qaware/cloudcomputingVorlesung Cloud Computing
JavaScript MIT License UpdatedJun 13, 2024 -
code-coverage-api-plugin Public
Forked from jenkinsci/code-coverage-api-pluginDeprecated Jenkins Code Coverage Plugin
Java MIT License UpdatedMay 1, 2024 -
core Public
Forked from home-assistant/core🏡 Open source home automation that puts local control and privacy first.
Python Apache License 2.0 UpdatedJun 13, 2024 -
cva6 Public
Forked from openhwgroup/cva6The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
SystemVerilog Other UpdatedAug 30, 2023 -
draw_uml Public
Forked from ogom/draw_umlDrawing the Unified Modeling Language of Rack
Ruby MIT License UpdatedSep 11, 2018 -
educational-materials Public
Forked from riscvarchive/educational-materialsEducational materials for RISC-V
UpdatedMar 26, 2021 -
esp Public
Forked from sld-columbia/espEmbedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
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hammer Public
Forked from ucb-bar/hammerHammer: Highly Agile Masks Made Effortlessly from RTL
Python BSD 3-Clause "New" or "Revised" License UpdatedJun 11, 2024 -
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ibex Public
Forked from lowRISC/ibexIbex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
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linux-on-litex-vexriscv Public
Forked from litex-hub/linux-on-litex-vexriscvLinux on LiteX-VexRiscv
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neorv32 Public
Forked from stnolting/neorv32🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
VHDL BSD 3-Clause "New" or "Revised" License UpdatedSep 19, 2023 -
noctegra.github.io Public
Forked from Noctegra/noctegra.github.ioHTML MIT License UpdatedFeb 11, 2019 -
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openasip Public
Forked from cpc/openasipOpen Application-Specific Instruction Set processor tools (OpenASIP)
C Other UpdatedApr 24, 2024 -
OpenLane Public
Forked from The-OpenROAD-Project/OpenLaneOpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Python Apache License 2.0 UpdatedMay 28, 2024 -
opensbi Public
Forked from riscv-software-src/opensbiRISC-V Open Source Supervisor Binary Interface
C Other UpdatedAug 24, 2023 -
opentitan Public
Forked from lowRISC/opentitanOpenTitan: Open source silicon root of trust
SystemVerilog Apache License 2.0 UpdatedJun 13, 2024 -
orconf Public
Forked from fossi-foundation/orconfOpenRISC Conference Website
HTML UpdatedSep 16, 2023 -
Piccolo Public
Forked from bluespec/PiccoloRISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
Verilog Apache License 2.0 UpdatedJan 23, 2022 -
Pipelined_CPU_RISC-V Public
Forked from baraba6u/Pipelined_CPU_RISC-VPipelined CPU for RISC-V architecture(RV32I)
Verilog GNU General Public License v3.0 UpdatedDec 3, 2022 -
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raven-picorv32 Public
Forked from efabless/raven-picorv32Silicon-validated SoC implementation of the PicoSoc/PicoRV32
Verilog Other UpdatedJul 28, 2020 -
RiftCore Public
Forked from whutddk/RiftCoreRiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System
Verilog Apache License 2.0 UpdatedSep 21, 2022 -
risc-666 Public
Forked from lcq2/risc-666RISC-V user-mode emulator that runs DooM
C++ GNU General Public License v3.0 UpdatedApr 27, 2019