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Next generation CGRA generator
Python 111 12
C++ 81 13
Python 55 9
SoC Based on ARM Cortex-M3
Verilog 29 12
Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory macros.
Python 21 2
Documentation for the entire CGRAFlow
19 3
Python bindings for coreir
The PE for the second generation CGRA (garnet).
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