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THU-DSP-LAB · May 23, 2024 · 40f9d29 · 40f9d29
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diff --git a/README.md b/README.md
@@ -1,4 +1,4 @@
-![](https://github.com/THU-DSP-LAB/ventus-gpgpu-verilog/blob/main/docs/images/ChinaCore_logo.jpg)
+![](https://github.com/THU-DSP-LAB/ventus-gpgpu-verilog/blob/docs/docs/images/ChinaCore_logo.jpg)
 
 # Ventus GPGPU(Verilog Edition)
 
@@ -14,15 +14,15 @@ Copyright (c) 2023-2024 C\*Core Technology Co.,Ltd,Suzhou.
 
 ## Architecture
 
-乘影的硬件架构文档在[这里](https://github.com/THU-DSP-LAB/ventus-gpgpu-verilog/blob/main/docs/ventus-gpgpu-verilog-release-v1.0-spec.pdf)
+乘影的硬件架构文档在[这里](https://github.com/THU-DSP-LAB/ventus-gpgpu-verilog/blob/docs/docs/ventus-gpgpu-verilog-release-v1.0-spec.pdf)
 
 承影的硬件结构框图如下所示:
 
-![](https://github.com/THU-DSP-LAB/ventus-gpgpu-verilog/blob/main/docs/images/ventus_verilog_arch1.png)
+![](https://github.com/THU-DSP-LAB/ventus-gpgpu-verilog/blob/docs/docs/images/ventus_verilog_arch1.png)
 
 SM核的硬件结构框图如下所示:
 
-![](https://github.com/THU-DSP-LAB/ventus-gpgpu-verilog/blob/main/docs/images/ventus_verilog_arch2.png)
+![](https://github.com/THU-DSP-LAB/ventus-gpgpu-verilog/blob/docs/docs/images/ventus_verilog_arch2.png)
 
 ## Getting started
 
@@ -49,7 +49,7 @@ make verdi
 
 ## Case Description
 
-![](https://github.com/THU-DSP-LAB/ventus-gpgpu-verilog/blob/main/docs/images/test_20240527.png)
+![](https://github.com/THU-DSP-LAB/ventus-gpgpu-verilog/blob/docs/docs/images/test_20240527.png)
 
 ## Acknowledgement
 

diff --git a/docs/images/ChinaCore_logo.jpg b/docs/images/ChinaCore_logo.jpg
diff --git a/docs/images/test_20240527.png b/docs/images/test_20240527.png
diff --git a/docs/images/ventus_verilog_arch1.png b/docs/images/ventus_verilog_arch1.png