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Remove repeat range for logic variables
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@alaindargelas
alaindargelas committed Sep 13, 2023
1 parent 6fc68a4 commit 08531de
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Showing 71 changed files with 22 additions and 2,647 deletions.
2 changes: 1 addition & 1 deletion .vscode/launch.json
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Expand Up @@ -837,7 +837,7 @@
"type": "cppdbg",
"request": "launch",
"program": "${workspaceFolder}/dbuild/bin/surelog",
"args": ["-parse", "tests/ScratchPad.sv", "-elabuhdm", "-d", "inst", "-synth", "-d", "ast", "-d", "uhdm", "-d", "uhdmstats", "-d", "vpi_ids", "-replay", "-nocache", "-nobuiltin"],
"args": ["-parse", "tests/ScratchPad.sv", "-d", "inst", "-synth", "-d", "ast", "-d", "uhdm", "-d", "uhdmstats", "-d", "vpi_ids", "-replay", "-nocache", "-nobuiltin"],
"stopAtEntry": false,
"cwd": "${workspaceFolder}",
"environment": [],
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4 changes: 3 additions & 1 deletion src/DesignCompile/ElaborationStep.cpp
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Expand Up @@ -1790,7 +1790,9 @@ any* ElaborationStep::makeVar_(DesignComponent* component, Signal* sig,
obj = stv;
} else if (tpstype == uhdmlogic_typespec) {
logic_var* stv = s.MakeLogic_var();
stv->Ranges(packedDimensions);
// Do not set packedDimensions, it is a repeat of the typespec packed
// dimension.
// stv->Ranges(packedDimensions);
obj = stv;
} else if (tpstype == uhdmenum_typespec) {
enum_var* stv = s.MakeEnum_var();
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20 changes: 0 additions & 20 deletions tests/AlwaysNoElab/AlwaysNoElab.log
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Expand Up @@ -1201,26 +1201,6 @@ design: (work@dut)
|vpiName:device_sel_req
|vpiFullName:[email protected]_sel_req
|vpiVisibility:1
|vpiRange:
\_range: , line:6:9, endln:6:31
|vpiParent:
\_logic_var: ([email protected]_sel_req), line:6:32, endln:6:46
|vpiLeftRange:
\_constant: , line:6:10, endln:6:26
|vpiParent:
\_range: , line:6:9, endln:6:31
|vpiDecompile:1
|vpiSize:64
|INT:1
|vpiConstType:7
|vpiRightRange:
\_constant: , line:6:29, endln:6:30
|vpiParent:
\_range: , line:6:9, endln:6:31
|vpiDecompile:0
|vpiSize:64
|UINT:0
|vpiConstType:9
|vpiVariables:
\_int_var: ([email protected]), line:7:7, endln:7:17
|vpiParent:
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40 changes: 0 additions & 40 deletions tests/Assertions/Assertions.log
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Expand Up @@ -791,26 +791,6 @@ design: (work@m)
|vpiName:a
|vpiFullName:[email protected]
|vpiVisibility:1
|vpiRange:
\_range: , line:2:7, endln:2:13
|vpiParent:
\_logic_var: ([email protected]), line:2:14, endln:2:15
|vpiLeftRange:
\_constant: , line:2:8, endln:2:10
|vpiParent:
\_range: , line:2:7, endln:2:13
|vpiDecompile:15
|vpiSize:64
|UINT:15
|vpiConstType:9
|vpiRightRange:
\_constant: , line:2:11, endln:2:12
|vpiParent:
\_range: , line:2:7, endln:2:13
|vpiDecompile:0
|vpiSize:64
|UINT:0
|vpiConstType:9
|vpiVariables:
\_logic_var: ([email protected]), line:2:17, endln:2:18
|vpiParent:
Expand All @@ -820,26 +800,6 @@ design: (work@m)
|vpiName:b
|vpiFullName:[email protected]
|vpiVisibility:1
|vpiRange:
\_range: , line:2:7, endln:2:13
|vpiParent:
\_logic_var: ([email protected]), line:2:17, endln:2:18
|vpiLeftRange:
\_constant: , line:2:8, endln:2:10
|vpiParent:
\_range: , line:2:7, endln:2:13
|vpiDecompile:15
|vpiSize:64
|UINT:15
|vpiConstType:9
|vpiRightRange:
\_constant: , line:2:11, endln:2:12
|vpiParent:
\_range: , line:2:7, endln:2:13
|vpiDecompile:0
|vpiSize:64
|UINT:0
|vpiConstType:9
|vpiVariables:
\_logic_var: ([email protected]), line:3:7, endln:3:8
|vpiParent:
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20 changes: 0 additions & 20 deletions tests/AssignSubs/AssignSubs.log
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Expand Up @@ -620,26 +620,6 @@ design: (work@dut)
|UINT:0
|vpiConstType:9
|vpiFullName:[email protected]
|vpiRange:
\_range: , line:12:8, endln:12:13
|vpiParent:
\_array_var: ([email protected]), line:12:14, endln:12:15
|vpiLeftRange:
\_constant: , line:12:9, endln:12:10
|vpiParent:
\_range: , line:12:8, endln:12:13
|vpiDecompile:3
|vpiSize:64
|UINT:3
|vpiConstType:9
|vpiRightRange:
\_constant: , line:12:11, endln:12:12
|vpiParent:
\_range: , line:12:8, endln:12:13
|vpiDecompile:0
|vpiSize:64
|UINT:0
|vpiConstType:9
|vpiTypedef:
\_enum_typespec: (pkg::priv_lvl_e), line:2:2, endln:4:16
|vpiTypedef:
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20 changes: 0 additions & 20 deletions tests/BiasValue/BiasValue.log
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Expand Up @@ -1170,26 +1170,6 @@ design: (work@bp_be_rec_to_fp)
|vpiName:wrong_range
|vpiFullName:work@bp_be_rec_to_fp.wrong_range
|vpiVisibility:1
|vpiRange:
\_range: , line:8:9, endln:8:25
|vpiParent:
\_logic_var: (work@bp_be_rec_to_fp.wrong_range), line:8:26, endln:8:37
|vpiLeftRange:
\_constant: , line:8:10, endln:8:21
|vpiParent:
\_range: , line:8:9, endln:8:25
|vpiDecompile:-1792
|vpiSize:64
|INT:-1792
|vpiConstType:7
|vpiRightRange:
\_constant: , line:8:23, endln:8:24
|vpiParent:
\_range: , line:8:9, endln:8:25
|vpiDecompile:0
|vpiSize:64
|UINT:0
|vpiConstType:9
|vpiParameter:
\_parameter: (work@bp_be_rec_to_fp.sp_exp_width_gp), line:2:14, endln:2:29
|vpiParent:
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20 changes: 0 additions & 20 deletions tests/BinarySize/BinarySize.log
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Expand Up @@ -305,26 +305,6 @@ design: (work@top)
|vpiName:first
|vpiFullName:[email protected]
|vpiVisibility:1
|vpiRange:
\_range: , line:2:15, endln:2:21
|vpiParent:
\_logic_var: ([email protected]), line:2:22, endln:2:27
|vpiLeftRange:
\_constant: , line:2:16, endln:2:18
|vpiParent:
\_range: , line:2:15, endln:2:21
|vpiDecompile:31
|vpiSize:64
|UINT:31
|vpiConstType:9
|vpiRightRange:
\_constant: , line:2:19, endln:2:20
|vpiParent:
\_range: , line:2:15, endln:2:21
|vpiDecompile:0
|vpiSize:64
|UINT:0
|vpiConstType:9
|vpiDefName:work@top
|vpiTop:1
|vpiTopModule:1
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20 changes: 0 additions & 20 deletions tests/Bindings/Bindings.log
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Original file line number Diff line number Diff line change
Expand Up @@ -3637,26 +3637,6 @@ design: (work@dut1)
|vpiName:device_sel_req
|vpiFullName:[email protected]_sel_req
|vpiVisibility:1
|vpiRange:
\_range: , line:25:9, endln:25:31
|vpiParent:
\_logic_var: ([email protected]_sel_req), line:25:32, endln:25:46
|vpiLeftRange:
\_constant: , line:25:10, endln:25:26
|vpiParent:
\_range: , line:25:9, endln:25:31
|vpiDecompile:0
|vpiSize:64
|INT:0
|vpiConstType:7
|vpiRightRange:
\_constant: , line:25:29, endln:25:30
|vpiParent:
\_range: , line:25:9, endln:25:31
|vpiDecompile:0
|vpiSize:64
|UINT:0
|vpiConstType:9
|vpiVariables:
\_int_var: ([email protected]), line:26:7, endln:26:17
|vpiParent:
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80 changes: 0 additions & 80 deletions tests/BitPartSelect/BitPartSelect.log
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Original file line number Diff line number Diff line change
Expand Up @@ -627,46 +627,6 @@ design: (work@top)
|vpiName:storage
|vpiFullName:[email protected]
|vpiVisibility:1
|vpiRange:
\_range: , line:5:10, endln:5:21
|vpiParent:
\_logic_var: ([email protected]), line:5:33, endln:5:40
|vpiLeftRange:
\_constant: , line:5:11, endln:5:16
|vpiParent:
\_range: , line:5:10, endln:5:21
|vpiDecompile:3
|vpiSize:64
|INT:3
|vpiConstType:7
|vpiRightRange:
\_constant: , line:5:19, endln:5:20
|vpiParent:
\_range: , line:5:10, endln:5:21
|vpiDecompile:0
|vpiSize:64
|UINT:0
|vpiConstType:9
|vpiRange:
\_range: , line:5:21, endln:5:32
|vpiParent:
\_logic_var: ([email protected]), line:5:33, endln:5:40
|vpiLeftRange:
\_constant: , line:5:22, endln:5:27
|vpiParent:
\_range: , line:5:21, endln:5:32
|vpiDecompile:15
|vpiSize:64
|INT:15
|vpiConstType:7
|vpiRightRange:
\_constant: , line:5:30, endln:5:31
|vpiParent:
\_range: , line:5:21, endln:5:32
|vpiDecompile:0
|vpiSize:64
|UINT:0
|vpiConstType:9
|vpiVariables:
\_logic_var: ([email protected]_rdata), line:6:22, endln:6:35
|vpiParent:
Expand Down Expand Up @@ -696,26 +656,6 @@ design: (work@top)
|vpiName:storage_rdata
|vpiFullName:[email protected]_rdata
|vpiVisibility:1
|vpiRange:
\_range: , line:6:10, endln:6:21
|vpiParent:
\_logic_var: ([email protected]_rdata), line:6:22, endln:6:35
|vpiLeftRange:
\_constant: , line:6:11, endln:6:16
|vpiParent:
\_range: , line:6:10, endln:6:21
|vpiDecompile:15
|vpiSize:64
|INT:15
|vpiConstType:7
|vpiRightRange:
\_constant: , line:6:19, endln:6:20
|vpiParent:
\_range: , line:6:10, endln:6:21
|vpiDecompile:0
|vpiSize:64
|UINT:0
|vpiConstType:9
|vpiVariables:
\_logic_var: ([email protected]_rptr), line:7:25, endln:7:34
|vpiParent:
Expand Down Expand Up @@ -747,26 +687,6 @@ design: (work@top)
|vpiName:fifo_rptr
|vpiFullName:[email protected]_rptr
|vpiVisibility:1
|vpiRange:
\_range: , line:7:9, endln:7:24
|vpiParent:
\_logic_var: ([email protected]_rptr), line:7:25, endln:7:34
|vpiLeftRange:
\_constant: , line:7:10, endln:7:19
|vpiParent:
\_range: , line:7:9, endln:7:24
|vpiDecompile:1
|vpiSize:64
|INT:1
|vpiConstType:7
|vpiRightRange:
\_constant: , line:7:22, endln:7:23
|vpiParent:
\_range: , line:7:9, endln:7:24
|vpiDecompile:0
|vpiSize:64
|UINT:0
|vpiConstType:9
|vpiParameter:
\_parameter: ([email protected]), line:2:27, endln:2:32
|vpiParent:
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20 changes: 0 additions & 20 deletions tests/BitsArray/BitsArray.log
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Expand Up @@ -602,26 +602,6 @@ design: (work@top)
|UINT:0
|vpiConstType:9
|vpiFullName:[email protected]_init_we
|vpiRange:
\_range: , line:13:10, endln:13:15
|vpiParent:
\_array_var: ([email protected]_init_we), line:13:16, endln:13:27
|vpiLeftRange:
\_constant: , line:13:11, endln:13:12
|vpiParent:
\_range: , line:13:10, endln:13:15
|vpiDecompile:7
|vpiSize:64
|UINT:7
|vpiConstType:9
|vpiRightRange:
\_constant: , line:13:13, endln:13:14
|vpiParent:
\_range: , line:13:10, endln:13:15
|vpiDecompile:0
|vpiSize:64
|UINT:0
|vpiConstType:9
|vpiDefName:work@top
|vpiTop:1
|vpiTopModule:1
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20 changes: 0 additions & 20 deletions tests/BitsLogic/BitsLogic.log
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Original file line number Diff line number Diff line change
Expand Up @@ -570,26 +570,6 @@ design: (work@top)
|vpiName:b
|vpiFullName:[email protected]
|vpiVisibility:1
|vpiRange:
\_range: , line:26:7, endln:26:14
|vpiParent:
\_logic_var: ([email protected]), line:26:15, endln:26:16
|vpiLeftRange:
\_constant: , line:26:8, endln:26:9
|vpiParent:
\_range: , line:26:7, endln:26:14
|vpiDecompile:11
|vpiSize:64
|INT:11
|vpiConstType:7
|vpiRightRange:
\_constant: , line:26:12, endln:26:13
|vpiParent:
\_range: , line:26:7, endln:26:14
|vpiDecompile:0
|vpiSize:64
|UINT:0
|vpiConstType:9
|vpiParameter:
\_parameter: ([email protected]), line:24:11, endln:24:12
|vpiParent:
Expand Down
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