verilog black box ports unknown/loads

Signed-off-by: James Cherry <[email protected]>
TimingPredict · Sep 17, 2021 · 85f437b · 85f437b
1 parent 41706e0
commit 85f437b
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Showing 2 changed files with 5 additions and 3 deletions.
diff --git a/network/Network.cc b/network/Network.cc
@@ -521,7 +521,9 @@ Network::isLoad(const Pin *pin) const
   const Instance *inst = instance(pin);
   return (isLeaf(inst) && dir->isAnyInput())
     // isTopLevelPort(pin)
-    || (isTopInstance(inst) && dir->isAnyOutput());
+    || (isTopInstance(inst) && dir->isAnyOutput())
+    // Black box unknown ports are treated as loads.
+    || dir->isUnknown();
 }
 
 bool

diff --git a/verilog/VerilogReader.cc b/verilog/VerilogReader.cc
@@ -2058,7 +2058,7 @@ VerilogReader::makeBlackBoxNamedPorts(Cell *cell,
     Port *port = (size == 1)
       ? network_->makePort(cell, port_name)
       : network_->makeBusPort(cell, port_name, 0, size - 1);
-    network_->setDirection(port, PortDirection::bidirect());
+    network_->setDirection(port, PortDirection::unknown());
   }
 }
 
@@ -2077,7 +2077,7 @@ VerilogReader::makeBlackBoxOrderedPorts(Cell *cell,
       ? network_->makePort(cell, port_name)
       : network_->makeBusPort(cell, port_name, size - 1, 0);
     stringDelete(port_name);
-    network_->setDirection(port, PortDirection::bidirect());
+    network_->setDirection(port, PortDirection::unknown());
     port_index++;
   }
 }