Skip to content

Commit

Permalink
2.0.6
Browse files Browse the repository at this point in the history
  • Loading branch information
jjcherry56 committed Jan 27, 2019
1 parent ca231b2 commit 3f65204
Show file tree
Hide file tree
Showing 34 changed files with 369 additions and 188 deletions.
2 changes: 1 addition & 1 deletion CMakeLists.txt
Original file line number Diff line number Diff line change
Expand Up @@ -16,7 +16,7 @@

cmake_minimum_required (VERSION 3.9)

project(STA VERSION 2.0.5)
project(STA VERSION 2.0.6)

set(CMAKE_VERBOSE_MAKEFILE ON)
set(CMAKE_CXX_STANDARD 11)
Expand Down
2 changes: 1 addition & 1 deletion configure.ac
Original file line number Diff line number Diff line change
Expand Up @@ -16,7 +16,7 @@

# Process this file with autoconf to produce a configure script.

AC_INIT(sta, 2.0.5)
AC_INIT(sta, 2.0.6)
AM_INIT_AUTOMAKE
AC_CONFIG_MACRO_DIR([m4])
AC_CONFIG_HEADERS(config.h)
Expand Down
3 changes: 2 additions & 1 deletion dcalc/ArcDelayCalc.hh
Original file line number Diff line number Diff line change
Expand Up @@ -84,7 +84,8 @@ public:
float load_cap,
Parasitic *drvr_parasitic,
float related_out_cap,
const Pvt *pvt, const DcalcAnalysisPt *dcalc_ap,
const Pvt *pvt,
const DcalcAnalysisPt *dcalc_ap,
// Return values.
ArcDelay &gate_delay,
Slew &drvr_slew) = 0;
Expand Down
17 changes: 9 additions & 8 deletions dcalc/ArnoldiDelayCalc.cc
Original file line number Diff line number Diff line change
Expand Up @@ -1309,7 +1309,8 @@ ArnoldiDelayCalc::ra_get_r(delay_work *D,
ArcDelay d1;
Slew s1;
tab->table->gateDelay(tab->cell, tab->pvt, tab->in_slew,
c1, tab->relcap, d1, s1);
c1, tab->relcap, pocv_enabled_,
d1, s1);
tlohi = slew_derate*delayAsFloat(s1);
r = tlohi/(c_log*c1);
if (rdelay>0.0 && r > rdelay)
Expand All @@ -1332,7 +1333,7 @@ ArnoldiDelayCalc::ra_get_s(delay_work *D,
ArcDelay d1;
Slew s1;
tab->table->gateDelay(tab->cell, tab->pvt, tab->in_slew,
c, tab->relcap, d1, s1);
c, tab->relcap, pocv_enabled_, d1, s1);
tlohi = slew_derate*delayAsFloat(s1);
smin = r*c*c_smin; // c_smin = ra_hinv((1-vhi)/vhi-log(vhi)) + log(vhi);
if (c_log*r*c >= tlohi) {
Expand Down Expand Up @@ -1366,9 +1367,9 @@ ArnoldiDelayCalc::ra_rdelay_1(timing_table *tab,
ArcDelay d1, d2;
Slew s1, s2;
tab->table->gateDelay(tab->cell, tab->pvt, tab->in_slew,
c1, tab->relcap, d1, s1);
c1, tab->relcap, pocv_enabled_, d1, s1);
tab->table->gateDelay(tab->cell, tab->pvt, tab->in_slew,
c2, tab->relcap, d2, s2);
c2, tab->relcap, pocv_enabled_, d2, s2);
double dt50 = delayAsFloat(d1)-delayAsFloat(d2);
if (dt50 <= 0.0)
return 0.0;
Expand Down Expand Up @@ -1421,20 +1422,20 @@ ArnoldiDelayCalc::ar1_ceff_delay(delay_work *D,
thix = ra_solve_for_t(p,s,vhi);
tlox = ra_solve_for_t(p,s,vlo);
tab->table->gateDelay(tab->cell, tab->pvt,tab->in_slew,
ctot, tab->relcap, df, sf);
ctot, tab->relcap, pocv_enabled_, df, sf);
debugPrint3(debug_, "arnoldi", 1,
"table slew (in_slew %s ctot %s) = %s\n",
units_->timeUnit()->asString(tab->in_slew),
units_->capacitanceUnit()->asString(ctot),
delayAsString(sf, units_));
delayAsString(sf, this));
tlohi = slew_derate*delayAsFloat(sf);
debugPrint2(debug_, "arnoldi", 1, "tlohi %s %s\n",
units_->timeUnit()->asString(tlohi),
units_->timeUnit()->asString(tlox-thix));
}
ceff = ctot;
tab->table->gateDelay(tab->cell, tab->pvt, tab->in_slew,
ceff, tab->relcap, df, sf);
ceff, tab->relcap, pocv_enabled_, df, sf);
t50_sy = delayAsFloat(df);
t50_sr = ra_solve_for_t(1.0/(r*ceff),s,0.5);

Expand Down Expand Up @@ -1476,7 +1477,7 @@ ArnoldiDelayCalc::ar1_ceff_delay(delay_work *D,
units_->capacitanceUnit()->asString(ceff));

tab->table->gateDelay(tab->cell, tab->pvt, tab->in_slew, ceff,
tab->relcap, df, sf);
tab->relcap, pocv_enabled_, df, sf);
t50_sy = delayAsFloat(df);
t50_sr = ra_solve_for_t(1.0/(r*ceff),s,0.5);
for (j=0;j<mod->n;j++) {
Expand Down
18 changes: 12 additions & 6 deletions dcalc/DmpCeff.cc
Original file line number Diff line number Diff line change
Expand Up @@ -77,7 +77,8 @@ gateModelRd(const LibertyCell *cell,
double c2,
double c1,
float related_out_cap,
const Pvt *pvt);
const Pvt *pvt,
bool pocv_enabled);
static bool
evalDmpEqnsState(void *state);
static void
Expand Down Expand Up @@ -378,6 +379,7 @@ DmpAlg::gateCapDelaySlew(double ceff,
static_cast<float>(in_slew_),
static_cast<float>(ceff),
related_out_cap_,
pocv_enabled_,
model_delay, model_slew);
delay = delayAsFloat(model_delay);
slew = delayAsFloat(model_slew);
Expand Down Expand Up @@ -1640,7 +1642,7 @@ DmpCeffDelayCalc::setCeffAlgorithm(const LibertyLibrary *drvr_library,
{
double rd = gate_model
? gateModelRd(drvr_cell, gate_model, in_slew, c2, c1,
related_out_cap, pvt)
related_out_cap, pvt, pocv_enabled_)
: 0.0;
// Zero Rd means the table is constant and thus independent of load cap.
if (rd < 1e-2
Expand Down Expand Up @@ -1726,7 +1728,8 @@ DmpCeffDelayCalc::reportGateDelay(const LibertyCell *drvr_cell,
if (model) {
float in_slew1 = delayAsFloat(in_slew);
model->reportGateDelay(drvr_cell, pvt, in_slew1, c_eff,
related_out_cap, digits, result);
related_out_cap, pocv_enabled_,
digits, result);
}
}

Expand All @@ -1737,15 +1740,18 @@ gateModelRd(const LibertyCell *cell,
double c2,
double c1,
float related_out_cap,
const Pvt *pvt)
const Pvt *pvt,
bool pocv_enabled)
{
float cap1 = static_cast<float>((c1 + c2) * .75);
float cap2 = cap1 * 1.1F;
float in_slew1 = static_cast<float>(in_slew);
ArcDelay d1, d2;
Slew s1, s2;
gate_model->gateDelay(cell, pvt, in_slew1, cap1, related_out_cap, d1, s1);
gate_model->gateDelay(cell, pvt, in_slew1, cap2, related_out_cap, d2, s2);
gate_model->gateDelay(cell, pvt, in_slew1, cap1, related_out_cap, pocv_enabled,
d1, s1);
gate_model->gateDelay(cell, pvt, in_slew1, cap2, related_out_cap, pocv_enabled,
d2, s2);
return abs(delayAsFloat(d1) - delayAsFloat(d2)) / (cap2 - cap1);
}

Expand Down
20 changes: 10 additions & 10 deletions dcalc/GraphDelayCalc1.cc
Original file line number Diff line number Diff line change
Expand Up @@ -846,9 +846,9 @@ GraphDelayCalc1::findInputArcDelay(LibertyCell *drvr_cell,
ArcDelay load_delay = gate_delay - intrinsic_delay;
debugPrint3(debug_, "delay_calc", 3,
" gate delay = %s intrinsic = %s slew = %s\n",
delayAsString(gate_delay, units_),
delayAsString(intrinsic_delay, units_),
delayAsString(gate_slew, units_));
delayAsString(gate_delay, this),
delayAsString(intrinsic_delay, this),
delayAsString(gate_slew, this));
graph_->setSlew(drvr_vertex, drvr_tr, ap_index, gate_slew);
annotateLoadDelays(drvr_vertex, drvr_tr, load_delay, false, dcalc_ap,
arc_delay_calc_);
Expand Down Expand Up @@ -1274,8 +1274,8 @@ GraphDelayCalc1::findArcDelay(LibertyCell *drvr_cell,
}
debugPrint2(debug_, "delay_calc", 3,
" gate delay = %s slew = %s\n",
delayAsString(gate_delay, units_),
delayAsString(gate_slew, units_));
delayAsString(gate_delay, this),
delayAsString(gate_slew, this));
// Merge slews.
const Slew &drvr_slew = graph_->slew(drvr_vertex, drvr_tr, ap_index);
if (delayFuzzyGreater(gate_slew, drvr_slew, dcalc_ap->slewMinMax())
Expand Down Expand Up @@ -1477,8 +1477,8 @@ GraphDelayCalc1::annotateLoadDelays(Vertex *drvr_vertex,
debugPrint3(debug_, "delay_calc", 3,
" %s load delay = %s slew = %s\n",
load_vertex->name(sdc_network_),
delayAsString(wire_delay, units_),
delayAsString(load_slew, units_));
delayAsString(wire_delay, this),
delayAsString(load_slew, this));
if (!load_vertex->slewAnnotated(drvr_tr, ap_index)) {
if (drvr_vertex->slewAnnotated(drvr_tr, ap_index)) {
// Copy the driver slew to the load if it is annotated.
Expand Down Expand Up @@ -1593,8 +1593,8 @@ GraphDelayCalc1::findCheckEdgeDelays(Edge *edge,
arc_set->role()->asString());
debugPrint2(debug_, "delay_calc", 3,
" from_slew = %s to_slew = %s\n",
delayAsString(from_slew, units_),
delayAsString(to_slew, units_));
delayAsString(from_slew, this),
delayAsString(to_slew, this));
float related_out_cap = 0.0;
if (related_out_pin) {
Parasitic *related_out_parasitic;
Expand All @@ -1616,7 +1616,7 @@ GraphDelayCalc1::findCheckEdgeDelays(Edge *edge,
check_delay);
debugPrint1(debug_, "delay_calc", 3,
" check_delay = %s\n",
delayAsString(check_delay, units_));
delayAsString(check_delay, this));
graph_->setArcDelay(edge, arc, ap_index, check_delay);
delay_changed = true;
}
Expand Down
11 changes: 6 additions & 5 deletions dcalc/LumpedCapDelayCalc.cc
Original file line number Diff line number Diff line change
Expand Up @@ -151,15 +151,15 @@ LumpedCapDelayCalc::gateDelay(const LibertyCell *drvr_cell,
GateTimingModel *model = gateModel(arc, dcalc_ap);
debugPrint3(debug_, "delay_calc", 3,
" in_slew = %s load_cap = %s related_load_cap = %s lumped\n",
delayAsString(in_slew, units()),
delayAsString(in_slew, this),
units()->capacitanceUnit()->asString(load_cap),
units()->capacitanceUnit()->asString(related_out_cap));
if (model) {
ArcDelay gate_delay1;
Slew drvr_slew1;
float in_slew1 = delayAsFloat(in_slew);
model->gateDelay(drvr_cell, pvt, in_slew1, load_cap, related_out_cap,
gate_delay1, drvr_slew1);
pocv_enabled_, gate_delay1, drvr_slew1);
gate_delay = gate_delay1;
drvr_slew = drvr_slew1;
drvr_slew_ = drvr_slew1;
Expand Down Expand Up @@ -245,7 +245,7 @@ LumpedCapDelayCalc::reportGateDelay(const LibertyCell *drvr_cell,
if (model) {
float in_slew1 = delayAsFloat(in_slew);
model->reportGateDelay(drvr_cell, pvt, in_slew1, load_cap,
related_out_cap, digits, result);
related_out_cap, false, digits, result);
}
}

Expand All @@ -264,7 +264,8 @@ LumpedCapDelayCalc::checkDelay(const LibertyCell *cell,
if (model) {
float from_slew1 = delayAsFloat(from_slew);
float to_slew1 = delayAsFloat(to_slew);
model->checkDelay(cell, pvt, from_slew1, to_slew1, related_out_cap, margin);
model->checkDelay(cell, pvt, from_slew1, to_slew1, related_out_cap,
false, margin);
}
else
margin = delay_zero;
Expand All @@ -287,7 +288,7 @@ LumpedCapDelayCalc::reportCheckDelay(const LibertyCell *cell,
float from_slew1 = delayAsFloat(from_slew);
float to_slew1 = delayAsFloat(to_slew);
model->reportCheckDelay(cell, pvt, from_slew1, from_slew_annotation, to_slew1,
related_out_cap, digits, result);
related_out_cap, false, digits, result);
}
}

Expand Down
9 changes: 1 addition & 8 deletions graph/Delay.cc
Original file line number Diff line number Diff line change
Expand Up @@ -22,18 +22,11 @@

namespace sta {

const char *
delayAsString(const Delay &delay,
const Units *units)
{
return delayAsString(delay, units, units->timeUnit()->digits());
}

const char *
delayAsString(const Delay &delay,
const StaState *sta)
{
return delayAsString(delay, sta->units(), sta->units()->timeUnit()->digits());
return delayAsString(delay, sta, sta->units()->timeUnit()->digits());
}

} // namespace
7 changes: 2 additions & 5 deletions graph/Delay.hh
Original file line number Diff line number Diff line change
Expand Up @@ -63,19 +63,16 @@ float
delaySigma2(const Delay &delay,
const EarlyLate *early_late);
const char *
delayAsString(const Delay &delay,
const Units *units);
const char *
delayAsString(const Delay &delay,
const StaState *sta);
const char *
delayAsString(const Delay &delay,
const Units *units,
const StaState *sta,
int digits);
const char *
delayAsString(const Delay &delay,
const EarlyLate *early_late,
const Units *units,
const StaState *sta,
int digits);
const Delay &
delayInitValue(const MinMax *min_max);
Expand Down
22 changes: 11 additions & 11 deletions graph/DelayFloat.cc
Original file line number Diff line number Diff line change
Expand Up @@ -148,29 +148,29 @@ delayRatio(const Delay &delay1,

const char *
delayAsString(const Delay &delay,
const Units *units,
const StaState *sta,
int digits)
{
return units->timeUnit()->asString(delay, digits);
}

float
delayAsFloat(const Delay &delay,
const EarlyLate *)
{
return delay;
return sta->units()->timeUnit()->asString(delay, digits);
}

const char *
delayAsString(const Delay &delay,
const EarlyLate *,
const Units *units,
const StaState *sta,
int digits)
{
const Unit *unit = units->timeUnit();
const Unit *unit = sta->units()->timeUnit();
return unit->asString(delay, digits);
}

float
delayAsFloat(const Delay &delay,
const EarlyLate *)
{
return delay;
}

float
delaySigma(const Delay &,
const EarlyLate *)
Expand Down
Loading

0 comments on commit 3f65204

Please sign in to comment.