Updated documentation.

VLSI-EDA · Nov 8, 2016 · f0bd8df · f0bd8df
1 parent 5b55394
commit f0bd8df
Show file tree

Hide file tree

Showing 4 changed files with 26 additions and 7 deletions.
diff --git a/...em/ddr3/ddr3_mem2mig_adapter_Spartan6.rst → ...em/ddr2/ddr2_mem2mig_adapter_Spartan6.rst b/...em/ddr3/ddr3_mem2mig_adapter_Spartan6.rst → ...em/ddr2/ddr2_mem2mig_adapter_Spartan6.rst
@@ -1,5 +1,5 @@
 
-ddr3_mem2mig_adapter_Spartan6
+ddr2_mem2mig_adapter_Spartan6
 #############################
 
 Adapter between the :doc:`PoC.Mem </References/Interfaces/Memory>`
@@ -30,13 +30,13 @@ Containts only combinational logic.
 
 .. rubric:: Entity Declaration:
 
-.. literalinclude:: ../../../../src/mem/ddr3/ddr3_mem2mig_adapter_Spartan6.vhdl
+.. literalinclude:: ../../../../src/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.vhdl
    :language: vhdl
    :tab-width: 2
    :linenos:
    :lines: 61-95
 
-Source file: `mem/ddr3/ddr3_mem2mig_adapter_Spartan6.vhdl <https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ddr3/ddr3_mem2mig_adapter_Spartan6.vhdl>`_
+Source file: `mem/ddr2/ddr2_mem2mig_adapter_Spartan6.vhdl <https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.vhdl>`_
 
 
 
diff --git a/docs/PoC/mem/ddr2/index.rst b/docs/PoC/mem/ddr2/index.rst
@@ -0,0 +1,21 @@
+ddr2
+====
+
+The namespace `PoC.mem.ddr2` is designated for own implementations of
+DDR2 memory controllers as well as for adapters for vendor-specific
+implementations. At the top-level, all controllers and adapters
+provide the same simple memory interface to the user application.
+
+.. **Package**
+
+**Entities**
+
+ * :doc:`PoC.mem.ddr2.mem2mig_adapter_Spartan6
+   <ddr2_mem2mig_adapter_Spartan6>` - Adapter for the Xilinx MIG core
+   for Spartan-6 FPGAs
+
+
+.. toctree::
+   :hidden:
+
+   ddr2_mem2mig_adapter_Spartan6
diff --git a/docs/PoC/mem/ddr3/index.rst b/docs/PoC/mem/ddr3/index.rst
@@ -13,13 +13,9 @@ provide the same simple memory interface to the user application.
  * :doc:`PoC.mem.ddr3.mem2mig_adapter_Series7
    <ddr3_mem2mig_adapter_Series7>` - Adapter for the Xilinx MIG core
    for 7-Series FPGAs
- * :doc:`PoC.mem.ddr3.mem2mig_adapter_Spartan6
-   <ddr3_mem2mig_adapter_Spartan6>` - Adapter for the Xilinx MIG core
-   for Spartan-6 FPGAs
 
 
 .. toctree::
    :hidden:
 
    ddr3_mem2mig_adapter_Series7
-   ddr3_mem2mig_adapter_Spartan6
diff --git a/docs/PoC/mem/index.rst b/docs/PoC/mem/index.rst
@@ -9,6 +9,7 @@ implementations.
 **Sub-Namespaces**
 
  * :doc:`PoC.mem.ddr3 <ddr3/index>` - DDR3 memory controllers
+ * :doc:`PoC.mem.ddr2 <ddr2/index>` - DDR2 memory controllers
  * :doc:`PoC.mem.is61lv <is61lv/index>` - ISSI - IS61LV SRAM controller
  * :doc:`PoC.mem.is61nlp <is61nlp/index>` - ISSI - IS61NLP SRAM controller
  * :doc:`PoC.mem.lut <lut/index>` - Lookup-Table (LUT) implementations
@@ -25,6 +26,7 @@ implementations.
    :hidden:
 
    ddr3/index
+   ddr2/index
    is61lv/index
    is61nlp/index
    lut/index