WRansohoff
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TwootBookGram Public
Simple demonstration of how to deploy a scalable web app which serves a small AI language model using cheap serverless cloud functions.
TypeScript MIT License UpdatedOct 31, 2024 -
heartbeat_asic Public
Example repository containing a simple counter, for use with the SiliconCompiler ASIC build system.
Python Apache License 2.0 UpdatedNov 15, 2023 -
nmigen_getting_started Public
A few basic designs to demonstrate the syntax for using nMigen's basic features.
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girih_tiles Public
CAD drawings of Girih tile shapes, with what I believe are accurate proportions
MIT License UpdatedFeb 19, 2023 -
OpenROAD Public
Forked from The-OpenROAD-Project/OpenROADOpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
Verilog BSD 3-Clause "New" or "Revised" License UpdatedFeb 6, 2023 -
STM32_UART_Examples Public
A few simple example projects demonstrating how to use some core features of STM32 UART peripherals.
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STM32_quickstart Public
Another 'quickstart' recipe for starting a new STM32-based GCC project. I've tried a few different project layouts for bare-metal C applications targeting Cortex-M microcontrollers, and this reposi…
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inkscape_purge_small_paths Public
Inkscape extension to remove small shapes from a vector image.
Python MIT License UpdatedMay 26, 2022 -
OpenFPGA Public
Forked from lnis-uofu/OpenFPGAAn Open-source FPGA IP Generator
C MIT License UpdatedAug 13, 2021 -
openlane Public
Forked from The-OpenROAD-Project/OpenLaneNOTE: The master branch is frozen for OpenMPW2. Please direct any PRs to the develop branch. :: OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Mag…
Verilog Apache License 2.0 UpdatedMay 10, 2021 -
STM32x0_timer_example Public
Example project demonstrating how to set up the core system clock and use it to drive a timer peripheral to blink an LED every second on an STM32F031K6 or STM32L031K6
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OpenROAD-flow-scripts Public
Forked from The-OpenROAD-Project/OpenROAD-flow-scriptsSourcePawn Other UpdatedMar 9, 2021 -
game_and_watch_fun Public
Repository containing code to run on a Nintendo Game and Watch.
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Magrat_v0 Public
Design files and test firmwares for a single-core STM32H7 board with extra RAM and a side of Flash.
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STM32F7_ramloaders Public
A couple of examples demonstrating how to run ephemeral programs in RAM and use Tightly-Coupled Memories on an STM32F723E Discovery Kit.
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STM32F723E_QSPI_Example Public
Example program demonstrating how to access Quad-SPI Flash chips using an STM32F723E Discovery Kit.
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STM32F723E_FMC_Examples Public
A few examples showing how to configure the STM32 external memory controller to communicate with the PSRAM and display on an STM32F723E Discovery Kit.
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STM32_ExternalMemory Public
Minimal example demonstrating how to map external memories to an STM32's internal memory space using its Quad-SPI and "Flexible Memory Controller" peripherals.
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rv32i_nmigen_blog Public
Minimal RISC-V RV32I CPU design as described in a companion blog post.
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nmigen_rv32i_min Public
Minimal work-in-progress implementation of a RISC-V CPU using nMigen. It supports the core RV32I instructions, but it is too large and still in-progress.
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MAX31855_breakout Public
Simple OSHW breakout board for a MAX31855 thermocouple amplifier chip.
C MIT License UpdatedMay 6, 2020 -
RFM95W_LoRa_test Public
Minimal STM32 application to demonstrate sending and receiving messages over LoRa using a HopeRF RFM95W radio module.
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nmigen-boards Public
Forked from amaranth-lang/amaranth-boardsBoard and connector definition files for nMigen
Python Other UpdatedApr 24, 2020 -
nmigen_ice40_spi_flash Public
Simple test application to read data out of an iCE40 FPGA board's SPI Flash chip.
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nmigen Public
Forked from amaranth-lang/amaranthA refreshed Python toolbox for building complex digital hardware
Python Other UpdatedMar 29, 2020 -
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ice40_blink Public
Simple "hello world" FPGA application to test running an nMigen design on an iCE40 chip.
Python MIT License UpdatedMar 20, 2020 -
stlink Public
Forked from stlink-org/stlinkstm32 discovery line linux programmer
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nmigen_cpu_test Public
Work-in-progress implementation of the educational "Beta CPU" from MIT's free online 6004.2x edX course, using the nMigen Python library as an HDL.
Python MIT License UpdatedMar 12, 2020 -
nmigen_alu_test Public
nMigen implementation of the simple ALU described in MIT's free 6004.1x online edX course. It's been a few years since college, so I'm brushing up on digital logic concepts. Eventually, I'd like to…
Python MIT License UpdatedMar 6, 2020