CorebootPayloadPkg DSC: Change the section alignment option

The current CorebootPayloadPkg will print the following message "InsertImageRecord - Section Alignment(0x20) is not 4K" during boot. It is caused by the section alignment arranged by the linker. This patch change the alignment to 4K for runtime drivers. Cc: Prince Agyeman <[email protected]> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Maurice Ma <[email protected]> Reviewed-by: Prince Agyeman <[email protected]>
WalonLi · Oct 26, 2016 · 937f5cb · 937f5cb
1 parent 200eaa3
commit 937f5cb
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diff --git a/CorebootPayloadPkg/CorebootPayloadPkg.fdf b/CorebootPayloadPkg/CorebootPayloadPkg.fdf
@@ -61,6 +61,7 @@ INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
 
 [FV.DXEFV]
 BlockSize          = 0x1000
+FvForceRebase      = FALSE
 FvAlignment        = 16
 ERASE_POLARITY     = 1
 MEMORY_MAPPED      = TRUE

diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
@@ -88,6 +88,9 @@
   INTEL:RELEASE_*_*_CC_FLAGS     = /D MDEPKG_NDEBUG
   MSFT:RELEASE_*_*_CC_FLAGS      = /D MDEPKG_NDEBUG
 
+[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
+  MSFT:*_*_*_DLINK_FLAGS         = /ALIGN:4096
+
 ################################################################################
 #
 # SKU Identification section - list of all SKU IDs supported by this Platform.

diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
@@ -90,6 +90,9 @@
   INTEL:RELEASE_*_*_CC_FLAGS     = /D MDEPKG_NDEBUG
   MSFT:RELEASE_*_*_CC_FLAGS      = /D MDEPKG_NDEBUG
 
+[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
+  MSFT:*_*_*_DLINK_FLAGS         = /ALIGN:4096
+
 ################################################################################
 #
 # SKU Identification section - list of all SKU IDs supported by this Platform.