PulseRain Reindeer - RISCV RV32I[M] Soft CPU

Verilog PCI express components

ISP-Lite, VIP, MIPI-RX IP实现，测试平台为KV260+AR1335 3MP@30fps

Hardware Assisted IEEE 1588 IP Core

A FPGA friendly 32 bit RISC-V CPU implementation

RISC-V Instruction Set Manual

A curated list of awesome smartnic tutorials, papers and projects.

An FPGA-based USB 1.1 (full-speed) device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB 1.1 (full-sp…

HDL libraries and projects

JPEG Encoder Verilog

High throughput JPEG decoder in Verilog for FPGA

Hardware Description Languages

Must-have verilog systemverilog modules

Verilator open-source SystemVerilog simulator and lint system

Icarus Verilog

Scala based HDL

OpenXuantie - OpenC910 Core

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目