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478 Open 1,346 Closed
478 Open 1,346 Closed
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Issues list

Wrong error message mentioning defparam when overriding localparam pending-verification This issue is pending verification and/or reproduction
#4927 opened Mar 3, 2025 by marzoul
Support user-defined primitives in the Verilog frontend and RTLIL feature-request
#4924 opened Mar 2, 2025 by taktoa
share: limit SAT effort feature-request
#4921 opened Feb 28, 2025 by widlarizer
share: replace activation patterns with more SAT feature-request
#4920 opened Feb 28, 2025 by widlarizer
Inconsistent simulation of assignment using undefined signals pending-verification This issue is pending verification and/or reproduction
#4919 opened Feb 28, 2025 by FSY369
1
Optimization depends on ordering of registers (if flattening is enabled) pending-verification This issue is pending verification and/or reproduction
#4913 opened Feb 23, 2025 by jurriaan
4
File references in docs should link to file on git documentation feature-request
#4912 opened Feb 21, 2025 by KrystalDelusion
splitcells causes an assert failure bug
#4909 opened Feb 20, 2025 by mattyoung101
3
Optimize opt_expr evaluation ordering feature-request
#4900 opened Feb 14, 2025 by KrystalDelusion
Problems with EDIF files when reading in vivado post-synthesis project pending-verification This issue is pending verification and/or reproduction
#4897 opened Feb 13, 2025 by teodor961
Convert power of 2 $pow cells to shift feature-request
#4896 opened Feb 12, 2025 by georgerennie
Continuous assign drives right-hand side pending-verification This issue is pending verification and/or reproduction
#4893 opened Feb 11, 2025 by rantvm
read_verilog never completes and continues to grow system memory usage bug
#4882 opened Feb 1, 2025 by gadfort
1
async2sync fails on check cells with async reset pending-verification This issue is pending verification and/or reproduction
#4875 opened Jan 29, 2025 by georgerennie
CXXRTL should warn or fail on unsupported clock features bug cxxrtl
#4874 opened Jan 29, 2025 by povik
4
Yosys will sometimes emit a flip-flop that never toggles instead of a constant 0
#4872 opened Jan 28, 2025 by leocassarani
2
Support for multi-line string for system verilog feature-request SystemVerilog Issues and questions related to SystemVerilog
#4871 opened Jan 28, 2025 by KelvinChung2000
Lexer prints token to stdout when multi-line string is attempted to be used bug
#4870 opened Jan 28, 2025 by widlarizer
1
Yosys synth_ice40 -dsp fails on an assertion bug
#4865 opened Jan 23, 2025 by zapta
2
Fail to detect FSM with specific writing style bug
#4861 opened Jan 21, 2025 by KelvinChung2000
2
Support gziped Liberty files feature-request
#4830 opened Jan 1, 2025 by hpretl
1
@widlarizer
17
Inconsistent simulation before and after synthesis of complex assignment expressions pending-verification This issue is pending verification and/or reproduction
#4828 opened Dec 24, 2024 by FSY369
16
Add an optional yosys start script feature-request
#4820 opened Dec 16, 2024 by widlarizer
1
synth_xilinx error in simple demo bug
#4816 opened Dec 13, 2024 by lehaifeng000
3
Deviation Between Yosys RTLIL EBNF Docs and RTLIL Lex/Yacc Frontend pending-verification This issue is pending verification and/or reproduction
#4811 opened Dec 10, 2024 by ThePerfectComputer
5
ProTip! Exclude everything labeled bug with -label:bug.