rv64v: fix vwsll's imm read and illegal vsew check (OpenXiangShan#3131)

src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala

@@ -465,13 +465,13 @@ class DecodeUnitComp()(implicit p : Parameters) extends XSModule with DecodeUnit
       /*
       i to vector move
        */
-      csBundle(0).srcType(0) := SrcType.reg
+      csBundle(0).srcType(0) := Mux(src1IsImm, SrcType.imm, SrcType.reg)
       csBundle(0).srcType(1) := SrcType.imm
       csBundle(0).srcType(2) := SrcType.imm
       csBundle(0).lsrc(1) := 0.U
       csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U
       csBundle(0).fuType := FuType.i2v.U
-      csBundle(0).fuOpType := Cat(IF2VectorType.iDup2Vec(2, 0), vsewReg)
+      csBundle(0).fuOpType := Cat(Mux(src1IsImm, IF2VectorType.immDup2Vec(2, 0), IF2VectorType.iDup2Vec(2, 0)), vsewReg)
       csBundle(0).vecWen := true.B
 
       for (i <- 0 until MAX_VLMUL / 2) {

src/main/scala/xiangshan/backend/decode/VTypeGen.scala

@@ -4,7 +4,7 @@ import org.chipsalliance.cde.config.Parameters
 import chisel3._
 import chisel3.util._
 import xiangshan._
-import xiangshan.backend.fu.vector.Bundles.VType
+import xiangshan.backend.fu.vector.Bundles.{VType, VsetVType}
 import xiangshan.backend.decode.isa.bitfield.{InstVType, Riscv32BitInst, XSInstBitFields}
 import xiangshan.backend.fu.VsetModule
 
@@ -50,7 +50,7 @@ class VTypeGen(implicit p: Parameters) extends XSModule{
   lastSpecVType := lastSpecVTypeNext
 
   private val instVType: InstVType = firstVsetInstField.ZIMM_VTYPE.asTypeOf(new InstVType)
-  private val vtypei: VType = VType.fromInstVType(instVType)
+  private val vtypei: VsetVType = VsetVType.fromInstVType(instVType)
 
   private val vsetModule = Module(new VsetModule)
   vsetModule.io.in.avl := 0.U

src/main/scala/xiangshan/backend/fu/Vsetu.scala

@@ -20,14 +20,14 @@ import org.chipsalliance.cde.config.Parameters
 import chisel3._
 import chisel3.util._
 import xiangshan._
-import xiangshan.backend.fu.vector.Bundles.{VConfig, VType, Vl}
+import xiangshan.backend.fu.vector.Bundles.{VConfig, VType, Vl, VSew, VLmul, VsetVType}
 
 class VsetModuleIO(implicit p: Parameters) extends XSBundle {
   private val vlWidth = p(XSCoreParamsKey).vlWidth
 
   val in = Input(new Bundle {
     val avl   : UInt = UInt(XLEN.W)
-    val vtype : VType = VType()
+    val vtype : VsetVType = VsetVType()
     val func  : UInt = FuOpType()
   })
 
@@ -76,7 +76,8 @@ class VsetModule(implicit p: Parameters) extends XSModule {
   println(s"[VsetModule] vlWidth: $vlWidth")
 
   private val log2Vlmul = vlmul
-  private val log2Vsew = vsew +& "b011".U
+  // use 2 bits vsew to store vsew
+  private val log2Vsew = vsew(VSew.width - 1, 0) +& "b011".U
 
   // vlen = 128, lmul = 8, sew = 8, log2Vlen = 7,
   // vlmul = b011, vsew = 0, 7 + 3 - (0 + 3) = 7
@@ -92,8 +93,8 @@ class VsetModule(implicit p: Parameters) extends XSModule {
   private val log2Elen = log2Up(ELEN)
   private val log2VsewMax = Mux(log2Vlmul(2), log2Elen.U + log2Vlmul, log2Elen.U)
 
-  private val sewIllegal = log2Vsew > log2VsewMax
-  private val lmulIllegal = vlmul === "b100".U
+  private val sewIllegal = VSew.isReserved(vsew) || (log2Vsew > log2VsewMax)
+  private val lmulIllegal = VLmul.isReserved(vlmul)
 
   private val illegal = lmulIllegal | sewIllegal | vtype.illegal
 

src/main/scala/xiangshan/backend/fu/vector/Bundles.scala

@@ -21,6 +21,20 @@ object Bundles {
     val vlmul   = VLmul()
   }
 
+  /**
+    * vset module's vtype bundle, use 3 bits vsew to check if it is illegal
+    *
+    * we need to get 3 bits vsew in Vtype struct, then vset module can check if it is reserved.
+    * and we use 2 bits to store vsew in other places to save space
+    */
+  class VsetVType(implicit p: Parameters) extends Bundle {
+    val illegal = Bool()
+    val vma     = Bool()
+    val vta     = Bool()
+    val vsew    = VtypeVSew()
+    val vlmul   = VLmul()
+  }
+
   object VType {
     def apply()(implicit p: Parameters) : VType = {
       new VType
@@ -57,6 +71,32 @@ object Bundles {
     }
   }
 
+  object VsetVType {
+    def apply()(implicit p: Parameters) : VsetVType = {
+      new VsetVType
+    }
+
+    def fromInstVType(instVType: InstVType)(implicit p: Parameters) : VsetVType = {
+      val res = Wire(VsetVType())
+      res.vma   := instVType.vma
+      res.vta   := instVType.vta
+      res.vsew  := instVType.vsew
+      res.vlmul := instVType.vlmul
+      res.illegal := false.B
+      res
+    }
+
+    def fromVtypeStruct(vtypeStruct: VtypeStruct)(implicit p: Parameters): VsetVType = {
+      val res = Wire(VsetVType())
+      res.illegal := vtypeStruct.vill
+      res.vma := vtypeStruct.vma
+      res.vta := vtypeStruct.vta
+      res.vsew := vtypeStruct.vsew
+      res.vlmul := vtypeStruct.vlmul
+      res
+    }
+  }
+
   class VConfig(implicit p: Parameters) extends Bundle {
     val vtype = new VType
     val vl    = Vl()
@@ -92,6 +132,8 @@ object Bundles {
     }
   }
 
+  object VtypeVSew extends NamedUInt(3)
+
   object VLmul extends NamedUInt(3) {
     def m1  : UInt = "b000".U(width.W)
     def m2  : UInt = "b001".U(width.W)

src/main/scala/xiangshan/backend/fu/wrapper/VSet.scala

@@ -6,7 +6,7 @@ import utility.ZeroExt
 import xiangshan.{VSETOpType, CSROpType}
 import xiangshan.backend.decode.Imm_VSETIVLI
 import xiangshan.backend.decode.isa.bitfield.InstVType
-import xiangshan.backend.fu.vector.Bundles.VType
+import xiangshan.backend.fu.vector.Bundles.VsetVType
 import xiangshan.backend.fu.{FuConfig, FuncUnit, PipedFuncUnit, VsetModule, VtypeStruct}
 import xiangshan.backend.fu.vector.Bundles.VConfig
 
@@ -25,8 +25,8 @@ class VSetBase(cfg: FuConfig)(implicit p: Parameters) extends PipedFuncUnit(cfg)
   protected val avl = Mux(VSETOpType.isVsetivli(in.ctrl.fuOpType), avlImm, in.data.src(0))
 
   protected val instVType: InstVType = Imm_VSETIVLI().getVType(in.data.src(1))
-  protected val vtypeImm: VType = VType.fromInstVType(instVType)
-  protected val vtype: VType = Mux(VSETOpType.isVsetvl(in.ctrl.fuOpType), VType.fromVtypeStruct(in.data.src(1).asTypeOf(new VtypeStruct())), vtypeImm)
+  protected val vtypeImm: VsetVType = VsetVType.fromInstVType(instVType)
+  protected val vtype: VsetVType = Mux(VSETOpType.isVsetvl(in.ctrl.fuOpType), VsetVType.fromVtypeStruct(in.data.src(1).asTypeOf(new VtypeStruct())), vtypeImm)
 
   vsetModule.io.in.func := in.ctrl.fuOpType
   connect0LatencyCtrlSingal