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  1. zhixuanchang.github.io zhixuanchang.github.io Public

    blog of ZhixuanChang

    HTML

  2. AXI4_Interconnect AXI4_Interconnect Public

    Forked from Verdvana/AXI4_Interconnect

    AXI总线连接器

    SystemVerilog

  3. zjuthesis zjuthesis Public

    Forked from TheNetAdmin/zjuthesis

    Zhejiang University Graduation Thesis LaTeX Template

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  4. ddr3-controller ddr3-controller Public

    Forked from someone755/ddr3-controller

    A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs

    Verilog

  5. hellopages hellopages Public

    test GitHub pages

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