基于Clash Core 制作的Clash For Linux备份仓库 A Clash For Linux Backup Warehouse Based on Clash Core

Open deep learning compiler stack for cpu, gpu and specialized accelerators

Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards

Tzer: TVM Implementation of "Coverage-Guided Tensor Compiler Fuzzing with Joint IR-Pass Mutation (OOPSLA'22)“.

Implementing Dijkstra's Algorithm in Software and Hardware

TVM Relay IR Visualization Tool (TVM 可视化工具)

HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators

Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory macros.

A list of ICs and IPs for AI, Machine Learning and Deep Learning.

A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs.

It can be used to build a programmable accelerator or an acccelerator for specific-mapping.

Productive and portable performance programming across spatial architectures (FPGAs, etc.) and vector architectures (GPUs, etc.)

Open source machine learning accelerators

CGRA-Flow is a integrated framework for CGRA synthesis and development.

An integrated CGRA design framework

Get started using Intel® FPGA tools on the Devcloud with tutorials, workshops, advanced courses, and sample projects built specifically for students, researchers, and developers. Visit our official…

Systolic array based simple TPU for CNN on PYNQ-Z2

Antmicro's fast, vendor-neutral DMA IP in Chisel

FRAME: Fast Roofline Analytical Modeling and Estimation

AXI4 to SRAM Interface

Chisel3 AXI FPU prototype

AKG (Auto Kernel Generator) is an optimizer for operators in Deep Learning Networks, which provides the ability to automatically fuse ops with specific patterns.

Bridging polyhedral analysis tools to the MLIR framework

Open-Source AXI4 DMA Engine in SystemVerilog and Chisel