HSD#16025128020 dts: arm64: intel: device tree configuration for agil…

…ex5 dwc3 enablement Add quirks required for dwc3 enablement for Agilex5 Signed-off-by: Adrian Ng Ho Yin <[email protected]>
altera-opensource · Aug 16, 2024 · 32a0a05 · 32a0a05
1 parent d451844
commit 32a0a05
Showing 1 changed file with 3 additions and 2 deletions.
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -1026,8 +1026,9 @@
 				iommus = <&smmu 7>;
 				phys = <&usbphy0>, <&usbphy0>;
 				phy-names = "usb2-phy", "usb3-phy";
-				maximum-speed = "super-speed-plus";
-				snps,dis_u2_sysphy-quirk;
+				maximum-speed = "super-speed";
+				snps,dis_u2_susphy_quirk;
+				snps,dis_u3_susphy_quirk;
 				snps,dma_set_40_bit_mask_quirk;
 			};
 		};