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1. pes_vending_machine pes_vending_machine Public

   The design and optimization of a vending machine FSM were accomplished using iVerilog, GTKwave, and Yosys

   Verilog 1

2. Adder_layered_tb Adder_layered_tb Public

   SystemVerilog 2

3. RTL_to_GDS_Cadence_flow RTL_to_GDS_Cadence_flow Public

   Tcl 1

4. Single-Cycle-RISC-V-Processor Single-Cycle-RISC-V-Processor Public

   This repository contains a single-cycle RISC-V processor designed in SystemVerilog for a 5th-semester project. It supports a subset of the RISC-V ISA and executes one instruction per clock cycle. T…

   SystemVerilog