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vsdflow
vsdflow PublicForked from kunalg123/vsdflow
VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using…
Verilog
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openlane_build_script
openlane_build_script PublicForked from nickson-jose/openlane_build_script
This script builds openlane and all its dependencies on an Ubuntu (only) System.
Shell
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vsdstdcelldesign
vsdstdcelldesign PublicForked from nickson-jose/vsdstdcelldesign
This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedures on how to create a custom LEF file and plugging it into an…
Verilog
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OpenLane
OpenLane PublicForked from efabless/OpenLane
NOTE: The master branch is frozen for OpenMPW2. Please direct any PRs to the develop branch. :: OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Mag…
Verilog
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caravel_user_project
caravel_user_project PublicForked from efabless/caravel_user_project
https://caravel-user-project.readthedocs.io
Verilog
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avsdpll_1v8
avsdpll_1v8 PublicForked from lakshmi-sathi/avsdpll_1v8
8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x multiplied clock at ~50% duty cycle on tt corner at room tempe…
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