Merge branch 'master' of git://www.denx.de/git/u-boot-imx

aurelianF · Sep 9, 2016 · 16f4166 · 16f4166
2 parents 01c5075 + d4ee504
commit 16f4166
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Showing 45 changed files with 1,576 additions and 56 deletions.
diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -35,6 +35,10 @@ choice
 	prompt "MX6 board select"
 	optional
 
+config TARGET_ADVANTECH_DMS_BA16
+	bool "Advantech dms-ba16"
+	select MX6Q
+
 config TARGET_ARISTAINETOS
 	bool "aristainetos"
 
@@ -200,6 +204,7 @@ config SYS_SOC
 	default "mx6"
 
 source "board/ge/bx50v3/Kconfig"
+source "board/advantech/dms-ba16/Kconfig"
 source "board/aristainetos/Kconfig"
 source "board/bachmann/ot1200/Kconfig"
 source "board/barco/platinum/Kconfig"

diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -1166,8 +1166,7 @@ void mx6_lpddr2_cfg(const struct mx6_ddr_sysinfo *sysinfo,
 	mmdc0->mpzqhwctrl = val;
 
 	/* Step 12: Configure and activate periodic refresh */
-	mmdc0->mdref = (0 << 14) | /* REF_SEL: Periodic refresh cycle: 64kHz */
-		       (3 << 11);  /* REFR: Refresh Rate - 4 refreshes */
+	mmdc0->mdref = (sysinfo->refsel << 14) | (sysinfo->refr << 11);
 
 	/* Step 13: Deassert config request - init complete */
 	mmdc0->mdscr = 0x00000000;
@@ -1472,8 +1471,7 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
 		MMDC1(mpzqhwctrl, val);
 
 	/* Step 12: Configure and activate periodic refresh */
-	mmdc0->mdref = (1 << 14) | /* REF_SEL: Periodic refresh cycle: 32kHz */
-		       (7 << 11);  /* REFR: Refresh Rate - 8 refreshes */
+	mmdc0->mdref = (sysinfo->refsel << 14) | (sysinfo->refr << 11);
 
 	/* Step 13: Deassert config request - init complete */
 	mmdc0->mdscr = 0x00000000;

diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
@@ -408,6 +408,8 @@ struct mx6_ddr_sysinfo {
 	u8 sde_to_rst;	/* Time from SDE enable until DDR reset# is high */
 	u8 pd_fast_exit;/* enable precharge powerdown fast-exit */
 	u8 ddr_type;	/* DDR type: DDR3(0) or LPDDR2(1) */
+	u8 refsel;	/* REF_SEL field of register MDREF */
+	u8 refr;	/* REFR field of register MDREF */
 };
 
 /*

diff --git a/board/advantech/dms-ba16/Kconfig b/board/advantech/dms-ba16/Kconfig
@@ -0,0 +1,31 @@
+if TARGET_ADVANTECH_DMS_BA16
+
+choice
+	prompt "DDR Size"
+	default SYS_DDR_2G
+
+config SYS_DDR_1G
+	bool "1GiB"
+
+config SYS_DDR_2G
+	bool "2GiB"
+
+endchoice
+
+config IMX_CONFIG
+	default "board/advantech/dms-ba16/dms-ba16_2g.cfg" if SYS_DDR_2G
+	default "board/advantech/dms-ba16/dms-ba16_1g.cfg" if SYS_DDR_1G
+
+config SYS_BOARD
+	default "dms-ba16"
+
+config SYS_VENDOR
+	default "advantech"
+
+config SYS_SOC
+	default "mx6"
+
+config SYS_CONFIG_NAME
+	default "advantech_dms-ba16"
+
+endif
diff --git a/board/advantech/dms-ba16/MAINTAINERS b/board/advantech/dms-ba16/MAINTAINERS
@@ -0,0 +1,8 @@
+ADVANTECH_DMS-BA16 BOARD
+M:	Akshay Bhat <[email protected]>
+M:	Ken Lin <[email protected]>
+S:	Maintained
+F:	board/advantech/dms-ba16/
+F:	include/configs/advantech_dms-ba16.h
+F:	configs/dms-ba16_defconfig
+F:	configs/dms-ba16-1g_defconfig
diff --git a/board/advantech/dms-ba16/Makefile b/board/advantech/dms-ba16/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright 2016 Timesys Corporation
+# Copyright 2016 Advantech Corporation
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := dms-ba16.o
diff --git a/board/advantech/dms-ba16/clocks.cfg b/board/advantech/dms-ba16/clocks.cfg
@@ -0,0 +1,25 @@
+/* set the default clock gate to save power */
+DATA 4, CCM_CCGR0, 0x00C03F3F
+DATA 4, CCM_CCGR1, 0x0030FC03
+DATA 4, CCM_CCGR2, 0x0FFFC000
+DATA 4, CCM_CCGR3, 0x3FF00000
+DATA 4, CCM_CCGR4, 0x00FFF300
+DATA 4, CCM_CCGR5, 0x0F0000C3
+DATA 4, CCM_CCGR6, 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
+DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
+
+/*
+ * Setup CCM_CCOSR register as follows:
+ *
+ * cko1_en  1    --> CKO1 enabled
+ * cko1_div 111  --> divide by 8
+ * cko1_sel 1011 --> ahb_clk_root
+ *
+ * This sets CKO1 at ahb_clk_root/8 132/8 16.5 MHz
+ */
+DATA 4, CCM_CCOSR, 0x000000fb
diff --git a/board/advantech/dms-ba16/ddr-setup.cfg b/board/advantech/dms-ba16/ddr-setup.cfg
@@ -0,0 +1,39 @@
+/* DDR IO */
+DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000c0000
+DATA 4, MX6_IOM_GRP_DDRPKE,   0x00000000
+DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000030
+DATA 4, MX6_IOM_DRAM_CAS,     0x00000030
+DATA 4, MX6_IOM_DRAM_RAS,     0x00000030
+DATA 4, MX6_IOM_GRP_ADDDS,    0x00000030
+DATA 4, MX6_IOM_DRAM_RESET,   0x00000030
+DATA 4, MX6_IOM_DRAM_SDBA2,   0x00000000
+DATA 4, MX6_IOM_DRAM_SDODT0,  0x00000030
+DATA 4, MX6_IOM_DRAM_SDODT1,  0x00000030
+DATA 4, MX6_IOM_GRP_CTLDS,    0x00000030
+DATA 4, MX6_IOM_DDRMODE_CTL,  0x00020000
+DATA 4, MX6_IOM_DRAM_SDQS0,   0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS1,   0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS2,   0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS3,   0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS4,   0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS5,   0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS6,   0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS7,   0x00000030
+DATA 4, MX6_IOM_GRP_DDRMODE,  0x00020000
+DATA 4, MX6_IOM_GRP_B0DS,     0x00000030
+DATA 4, MX6_IOM_GRP_B1DS,     0x00000030
+DATA 4, MX6_IOM_GRP_B2DS,     0x00000030
+DATA 4, MX6_IOM_GRP_B3DS,     0x00000030
+DATA 4, MX6_IOM_GRP_B4DS,     0x00000030
+DATA 4, MX6_IOM_GRP_B5DS,     0x00000030
+DATA 4, MX6_IOM_GRP_B6DS,     0x00000030
+DATA 4, MX6_IOM_GRP_B7DS,     0x00000030
+DATA 4, MX6_IOM_DRAM_DQM0,    0x00000030
+DATA 4, MX6_IOM_DRAM_DQM1,    0x00000030
+DATA 4, MX6_IOM_DRAM_DQM2,    0x00000030
+DATA 4, MX6_IOM_DRAM_DQM3,    0x00000030
+DATA 4, MX6_IOM_DRAM_DQM4,    0x00000030
+DATA 4, MX6_IOM_DRAM_DQM5,    0x00000030
+DATA 4, MX6_IOM_DRAM_DQM6,    0x00000030
+DATA 4, MX6_IOM_DRAM_DQM7,    0x00000030