Skip to content
View badcook's full-sized avatar

Block or report badcook

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
Showing results

ABC: System for Sequential Logic Synthesis and Formal Verification

C 956 611 Updated Mar 19, 2025

The Ultra-Low Power RISC-V Core

Verilog 1,439 360 Updated Oct 9, 2024