issue38 ccs_sim1

Signed-off-by: James Cherry <[email protected]>
bingyuew · Jun 5, 2024 · e81d3c5 · e81d3c5
1 parent b98f44c
commit e81d3c5
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Showing 2 changed files with 3 additions and 3 deletions.
diff --git a/dcalc/CcsSimDelayCalc.cc b/dcalc/CcsSimDelayCalc.cc
@@ -226,6 +226,8 @@ CcsSimDelayCalc::gateDelays(ArcDcalcArgSeq &dcalc_args,
   else {
     simulate(dcalc_args);
 
+    ArcDcalcArg &drvr_arg = dcalc_args[0];
+    const LibertyLibrary *drvr_library = drvr_arg.drvrLibrary();
     for (size_t drvr_idx = 0; drvr_idx < dcalc_args.size(); drvr_idx++) {
       ArcDcalcArg &dcalc_arg = dcalc_args[drvr_idx];
       ArcDcalcResult &dcalc_result = dcalc_results[drvr_idx];
@@ -258,8 +260,6 @@ CcsSimDelayCalc::gateDelays(ArcDcalcArgSeq &dcalc_args,
                    delayAsString(wire_delay, this),
                    delayAsString(load_slew, this));
 
-        LibertyLibrary *drvr_library =
-          network_->libertyPort(load_pin)->libertyCell()->libertyLibrary();
         thresholdAdjust(load_pin, drvr_library, drvr_rf_, wire_delay, load_slew);
         dcalc_result.setWireDelay(load_idx, wire_delay);
         dcalc_result.setLoadSlew(load_idx, load_slew);

diff --git a/test/regression.tcl b/test/regression.tcl
@@ -187,7 +187,7 @@ proc run_test { test } {
 	  puts " pass$error_msg"
 	}
       } else {
-	puts " *NO OK FILE*$error_msg"
+        puts " *NO OK FILE*"
 	append_failure $test
 	incr errors(no_ok)
       }