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ppc4xx: Remove 4xx NAND booting support
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As ppc4xx currently only supports the deprecated nand_spl infrastructure
and nobody seems to have time / resources to port this over to the newer
SPL infrastructure, lets remove NAND booting completely.

This should not affect the "normal", non NAND-booting ppc4xx platforms
that are currently supported.

Signed-off-by: Stefan Roese <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Tirumala Marri <[email protected]>
Cc: Matthias Fuchs <[email protected]>
Cc: Masahiro Yamada <[email protected]>
Cc: Tom Rini <[email protected]>
Tested-by: Matthias Fuchs <[email protected]>
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@stroese @trini
stroese authored and trini committed Mar 7, 2014
1 parent dc116bd commit 345b77b
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Showing 42 changed files with 15 additions and 1,882 deletions.
20 changes: 0 additions & 20 deletions arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
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Original file line number Diff line number Diff line change
Expand Up @@ -49,7 +49,6 @@
"SDRAM_" #mnemonic, SDRAM_##mnemonic, data); \
} while (0)

#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
static void update_rdcc(void)
{
u32 val;
Expand All @@ -72,7 +71,6 @@ static void update_rdcc(void)
}
}
}
#endif

#if defined(CONFIG_440)
/*
Expand Down Expand Up @@ -101,7 +99,6 @@ void dcbz_area(u32 start_address, u32 num_bytes);

#define MULDIV64(m1, m2, d) (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))

#if !defined(CONFIG_NAND_SPL)
/*-----------------------------------------------------------------------------+
* sdram_memsize
*-----------------------------------------------------------------------------*/
Expand Down Expand Up @@ -217,7 +214,6 @@ void board_add_ram_info(int use_default)
val = (val & SDRAM_MMODE_DCL_MASK) >> 4;
printf(", CL%d)", val);
}
#endif /* !CONFIG_NAND_SPL */

#if defined(CONFIG_SPD_EEPROM)

Expand Down Expand Up @@ -2843,16 +2839,6 @@ static void test(void)
*---------------------------------------------------------------------------*/
phys_size_t initdram(int board_type)
{
/*
* Only run this SDRAM init code once. For NAND booting
* targets like Kilauea, we call initdram() early from the
* 4k NAND booting image (CONFIG_NAND_SPL) from nand_boot().
* Later on the NAND U-Boot image runs (CONFIG_NAND_U_BOOT)
* which calls initdram() again. This time the controller
* mustn't be reconfigured again since we're already running
* from SDRAM.
*/
#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
unsigned long val;

#if defined(CONFIG_440)
Expand Down Expand Up @@ -2969,12 +2955,10 @@ phys_size_t initdram(int board_type)
#endif

#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
/*------------------------------------------------------------------
| DQS calibration.
+-----------------------------------------------------------------*/
DQS_autocalibration();
#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
#endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */

/*
Expand Down Expand Up @@ -3009,13 +2993,10 @@ phys_size_t initdram(int board_type)
set_mcsr(get_mcsr());
#endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */

#endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */

return (CONFIG_SYS_MBYTES_SDRAM << 20);
}
#endif /* CONFIG_SPD_EEPROM */

#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#if defined(CONFIG_440)
u32 mfdcr_any(u32 dcr)
{
Expand Down Expand Up @@ -3062,7 +3043,6 @@ void mtdcr_any(u32 dcr, u32 val)
}
}
#endif /* defined(CONFIG_440) */
#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */

inline void ppc4xx_ibm_ddr2_register_dump(void)
{
Expand Down
12 changes: 0 additions & 12 deletions arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
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Original file line number Diff line number Diff line change
Expand Up @@ -27,12 +27,6 @@

#include "ecc.h"

/*
* Only compile the DDR auto-calibration code for NOR boot and
* not for NAND boot (NAND SPL and NAND U-Boot - NUB)
*/
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)

#define MAXBXCF 4
#define SDRAM_RXBAS_SHIFT_1M 20

Expand Down Expand Up @@ -1231,9 +1225,3 @@ u32 DQS_autocalibration(void)

return 0;
}
#else /* defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
u32 DQS_autocalibration(void)
{
return 0;
}
#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
4 changes: 0 additions & 4 deletions arch/powerpc/cpu/ppc4xx/Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -14,11 +14,7 @@ obj-y += kgdb.o

obj-y += 40x_spd_sdram.o

ifndef CONFIG_NAND_SPL
ifndef CONFIG_NAND_U_BOOT
obj-y += 44x_spd_ddr.o
endif
endif
obj-$(CONFIG_SDRAM_PPC4xx_IBM_DDR2) += 44x_spd_ddr2.o
obj-$(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) += 4xx_ibm_ddr2_autocalib.o
obj-y += 4xx_pci.o
Expand Down
111 changes: 5 additions & 106 deletions arch/powerpc/cpu/ppc4xx/start.S
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Original file line number Diff line number Diff line change
Expand Up @@ -182,16 +182,13 @@


.extern ext_bus_cntlr_init
#ifdef CONFIG_NAND_U_BOOT
.extern reconfig_tlb0
#endif

/*
* Set up GOT: Global Offset Table
*
* Use r12 to access the GOT
*/
#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
#if !defined(CONFIG_SPL_BUILD)
START_GOT
GOT_ENTRY(_GOT2_TABLE_)
GOT_ENTRY(_FIXUP_TABLE_)
Expand All @@ -205,22 +202,7 @@
GOT_ENTRY(__bss_end)
GOT_ENTRY(__bss_start)
END_GOT
#endif /* CONFIG_NAND_SPL */

#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \
!defined(CONFIG_SPL_BUILD)
/*
* NAND U-Boot image is started from offset 0
*/
.text
#if defined(CONFIG_440)
bl reconfig_tlb0
#endif
GET_GOT
bl cpu_init_f /* run low-level CPU init code (from Flash) */
bl board_init_f
/* NOTREACHED - board_init_f() does not return */
#endif
#endif /* CONFIG_SPL_BUILD */

#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_BOOT_FROM_XMD)
/*
Expand Down Expand Up @@ -255,9 +237,7 @@
*/

#if defined(CONFIG_440)
#if !defined(CONFIG_NAND_SPL)
.section .bootpg,"ax"
#endif
.globl _start_440

/**************************************************************************/
Expand Down Expand Up @@ -511,7 +491,7 @@ tlbnx2: addi r4,r4,1 /* Next TLB */
* r3 - 1st arg to board_init(): IMMP pointer
* r4 - 2nd arg to board_init(): boot flag
*/
#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
#if !defined(CONFIG_SPL_BUILD)
.text
.long 0x27051956 /* U-Boot Magic Number */
.globl version_string
Expand Down Expand Up @@ -777,17 +757,13 @@ _start:
stwu r1,-8(r1) /* Save back chain and move SP */
stw r0,+12(r1) /* Save return addr (underflow vect) */

#ifdef CONFIG_NAND_SPL
bl nand_boot_common /* will not return */
#else
#ifndef CONFIG_SPL_BUILD
GET_GOT
#endif

bl cpu_init_f /* run low-level CPU init code (from Flash) */
bl board_init_f
/* NOTREACHED - board_init_f() does not return */
#endif

#endif /* CONFIG_440 */

Expand Down Expand Up @@ -1050,23 +1026,18 @@ _start:
stw r0, +12(r1) /* Save return addr (underflow vect) */
#endif /* CONFIG_SYS_INIT_DCACHE_CS */

#ifdef CONFIG_NAND_SPL
bl nand_boot_common /* will not return */
#else
GET_GOT /* initialize GOT access */

bl cpu_init_f /* run low-level CPU init code (from Flash) */

bl board_init_f /* run first part of init code (from Flash) */
/* NOTREACHED - board_init_f() does not return */

#endif /* CONFIG_NAND_SPL */

#endif /* CONFIG_405GP || CONFIG_405 || CONFIG_405EP */
/*----------------------------------------------------------------------- */


#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
#if !defined(CONFIG_SPL_BUILD)
/*
* This code finishes saving the registers to the exception frame
* and jumps to the appropriate handler for the exception.
Expand Down Expand Up @@ -1632,7 +1603,7 @@ __440_msr_continue:
blr
function_epilog(dcbz_area)
#endif /* CONFIG_440 */
#endif /* CONFIG_NAND_SPL */
#endif /* CONFIG_SPL_BUILD */

/*------------------------------------------------------------------------------- */
/* Function: in8 */
Expand Down Expand Up @@ -1981,75 +1952,3 @@ pll_wait:
blr
function_epilog(mftlb1)
#endif /* CONFIG_440 */

#if defined(CONFIG_NAND_SPL)
/*
* void nand_boot_relocate(dst, src, bytes)
*
* r3 = Destination address to copy code to (in SDRAM)
* r4 = Source address to copy code from
* r5 = size to copy in bytes
*/
nand_boot_relocate:
mr r6,r3
mr r7,r4
mflr r8

/*
* Copy SPL from icache into SDRAM
*/
subi r3,r3,4
subi r4,r4,4
srwi r5,r5,2
mtctr r5
..spl_loop:
lwzu r0,4(r4)
stwu r0,4(r3)
bdnz ..spl_loop

/*
* Calculate "corrected" link register, so that we "continue"
* in execution in destination range
*/
sub r3,r7,r6 /* r3 = src - dst */
sub r8,r8,r3 /* r8 = link-reg - (src - dst) */
mtlr r8
blr

nand_boot_common:
/*
* First initialize SDRAM. It has to be available *before* calling
* nand_boot().
*/
lis r3,CONFIG_SYS_SDRAM_BASE@h
ori r3,r3,CONFIG_SYS_SDRAM_BASE@l
bl initdram

/*
* Now copy the 4k SPL code into SDRAM and continue execution
* from there.
*/
lis r3,CONFIG_SYS_NAND_BOOT_SPL_DST@h
ori r3,r3,CONFIG_SYS_NAND_BOOT_SPL_DST@l
lis r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@h
ori r4,r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@l
lis r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@h
ori r5,r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@l
bl nand_boot_relocate

/*
* We're running from SDRAM now!!!
*
* It is necessary for 4xx systems to relocate from running at
* the original location (0xfffffxxx) to somewhere else (SDRAM
* preferably). This is because CS0 needs to be reconfigured for
* NAND access. And we can't reconfigure this CS when currently
* "running" from it.
*/

/*
* Finally call nand_boot() to load main NAND U-Boot image from
* NAND and jump to it.
*/
bl nand_boot /* will not return */
#endif /* CONFIG_NAND_SPL */
13 changes: 0 additions & 13 deletions board/amcc/acadia/memory.c
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Original file line number Diff line number Diff line change
Expand Up @@ -17,7 +17,6 @@

extern void board_pll_init_f(void);

#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
static void cram_bcr_write(u32 wr_val)
{
wr_val <<= 2;
Expand All @@ -41,20 +40,9 @@ static void cram_bcr_write(u32 wr_val)

return;
}
#endif

phys_size_t initdram(int board_type)
{
#if defined(CONFIG_NAND_SPL)
u32 reg;

/* don't reinit PLL when booting via I2C bootstrap option */
mfsdr(SDR0_PINSTP, reg);
if (reg != 0xf0000000)
board_pll_init_f();
#endif

#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
int i;
u32 val;

Expand Down Expand Up @@ -88,7 +76,6 @@ phys_size_t initdram(int board_type)
/* Wait a short while, since for NAND booting this is too fast */
for (i=0; i<200000; i++)
;
#endif

return (CONFIG_SYS_MBYTES_RAM << 20);
}
42 changes: 0 additions & 42 deletions board/amcc/acadia/pll.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -135,45 +135,3 @@ void board_pll_init_f(void)
mtcpr(CPR0_CLKUP, 0x40000000);
}
#endif /* CPU_<speed>_405EZ */

#if defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL)
/*
* Get timebase clock frequency
*/
unsigned long get_tbclk(void)
{
unsigned long cpr_plld;
unsigned long cpr_primad;
unsigned long primad_cpudv;
unsigned long pllFbkDiv;
unsigned long freqProcessor;

/*
* Read PLL Mode registers
*/
mfcpr(CPR0_PLLD, cpr_plld);

/*
* Read CPR_PRIMAD register
*/
mfcpr(CPR0_PRIMAD, cpr_primad);

/*
* Determine CPU clock frequency
*/
primad_cpudv = ((cpr_primad & PRIMAD_CPUDV_MASK) >> 24);
if (primad_cpudv == 0)
primad_cpudv = 16;

/*
* Determine FBK_DIV.
*/
pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24);
if (pllFbkDiv == 0)
pllFbkDiv = 256;

freqProcessor = (CONFIG_SYS_CLK_FREQ * pllFbkDiv) / primad_cpudv;

return (freqProcessor);
}
#endif /* defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL) */
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