MPC824x: remove obsolete "PN62" board

The MPC824x processors have long reached EOL, and the PN62 board has
not seen any board-specific updates for more than a decade.  It is now
causing build issues.  Instead of wasting time on things nobody is
interested in any more, we rather drop this board.

Signed-off-by: Wolfgang Denk <[email protected]>
Cc: Wolfgang Grandegger <[email protected]>
cc: Tom Rini <[email protected]>

CREDITS

@@ -143,7 +143,7 @@ W: www.freescale.com
 
 N: Dr. Wolfgang Grandegger
 E: [email protected]
-D: Support for Interphase 4539 T1/E1/J1 PMC, PN62, CCM, SCM boards
+D: Support for Interphase 4539 T1/E1/J1 PMC, CCM, SCM boards
 W: www.denx.de
 
 N: Peter Figuli

arch/powerpc/cpu/mpc824x/cpu_init.c

@@ -52,7 +52,7 @@ cpu_init_f (void)
     CONFIG_WRITE_HALFWORD(PCICR, 0x06); /* Bus Master, respond to PCI memory space acesses*/
 /*    CONFIG_WRITE_HALFWORD(PCISR, 0xffff); */ /*reset PCISR*/
 
-#if defined(CONFIG_MUSENKI) || defined(CONFIG_PN62)
+#if defined(CONFIG_MUSENKI)
 /* Why is this here, you ask?  Try, just try setting 0x8000
  * in PCIACR with CONFIG_WRITE_HALFWORD()
  * this one was a stumper, and we are annoyed
@@ -142,9 +142,7 @@ cpu_init_f (void)
 
 	CONFIG_READ_WORD(PICR2, val);
 	val= val & ~ (PICR2_CF_SNOOP_WS_MASK | PICR2_CF_APHASE_WS_MASK); /*mask off waitstate bits*/
-#ifndef CONFIG_PN62
 	val |= PICR2_CF_SNOOP_WS_1WS | PICR2_CF_APHASE_WS_1WS; /*1 wait state*/
-#endif
 	CONFIG_WRITE_WORD(PICR2, val);
 
 	CONFIG_WRITE_WORD(EUMBBAR, CONFIG_SYS_EUMB_ADDR);
@@ -186,7 +184,7 @@ cpu_init_f (void)
  *  should define CONFIG_SYS_ACTORW to 0 if they don't want to set it, or even, if
  *  its not set, we define it to zero in this file
  */
-#if defined(CONFIG_CU824) || defined(CONFIG_PN62)
+#if defined(CONFIG_CU824)
 	CONFIG_WRITE_WORD(MCCR4,
 	(CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) |
 	(CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) |